Concurrent Error Correction for Storage Data Transfer Latency

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Solution Overview

Problem

Current interfaces in computer systems, such as SATA, limit data transfer rates due to latency and overhead from error detection and correction, as well as encoding overhead, which restricts the throughput between storage devices and the host.

Innovation Solution

A system that transfers data from a storage device to a host using a PCIe interface, performing error detection and correction concurrently with data transfer, allowing blocks to be retransmitted out-of-order once errors are corrected, thereby reducing latency and increasing bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error detection and correction are performed prior to data transmission over SATA interface, then data reliability is improved, but transmission latency increases and throughput decreases

Engineering Contradiction:
Improvedata reliabilityVSAvoidtransmission latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs error detection and correction in advance during the data preparation phase, before data is queued for transmission. This preliminary action ensures that when data is transmitted over the SATA interface, it is already validated and corrected, eliminating the need for retransmissions and reducing overall transmission latency while maintaining data reliability

Inventive Principle:
Principle #10Preliminary action

2Reliability

If error detection and correction are performed prior to data transmission, then data reliability is improved, but effective throughput decreases due to processing overhead

Engineering Contradiction:
Improvedata reliabilityVSAvoideffective throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements continuous error detection and correction processing that operates in parallel with data preparation and queuing operations. This continuous processing ensures that error checking does not create idle time or bottlenecks in the data flow, maintaining high effective throughput while ensuring data reliability through persistent validation and correction capabilities

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

By performing error detection and correction before data enters the transmission queue, the system eliminates the need for post-transmission error handling and retransmissions, thereby maximizing effective throughput while maintaining data reliability

Inventive Principle:
Principle #10Preliminary action

3Reliability

If 8b/10b encoding is applied to transmitted data, then data integrity is improved, but interface overhead increases reducing effective throughput

Engineering Contradiction:
Improvedata integrityVSAvoideffective throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts and removes unnecessary overhead elements from the data transmission process by optimizing the encoding scheme and eliminating redundant validation steps that do not contribute to data integrity, thereby reducing interface overhead and improving effective throughput while maintaining essential data integrity protections

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9015557B2Simultaneous data transfer and error control to reduce latency and improve throughput to a host
Publication Date: 2015.04.21 APPLE INC
  • US9015557B2 patent drawing
  • US9015557B2 patent drawing
  • US9015557B2 patent drawing

AI summary

The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.