Concurrent Fault Co-Simulator for EDA Verification Efficiency
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Solution Overview
Problem
Current electronic design automation (EDA) systems face inefficiencies in performing combined functional and fault verification, requiring significant time and computational resources due to the complexity of serial fault simulation and manual processes, which are prone to errors and unable to accommodate changes in fault behavior effectively.
Innovation Solution
The integration of concurrent fault co-simulation within the EDA process flow allows for simultaneous functional and fault verification, reusing shared resources and calculating fault analysis as a difference from functional analysis, thereby reducing redundant calculations and simplifying the setup by identifying divergence points between functional and fault analysis in circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial fault simulation is performed separately from functional verification, then fault analysis can be conducted, but verification time and computational resources are significantly increased
Solution Approach 1:
The patent combines fault simulation and functional verification into a single concurrent co-simulation process. The co-simulator integrates both verification types by sharing common infrastructure including event queues, simulation time management, and circuit state tracking, allowing simultaneous execution rather than separate serial processes.
Solution Approach 2:
The co-simulator is designed as a universal platform that handles both functional verification and fault simulation through a unified architecture. It uses a common event queue system that can process both functional events and fault injection events, eliminating the need for separate verification environments.
2Reliability
If separate verification environments are created for functional and fault analysis, then each can be optimized independently, but device complexity and setup effort increase significantly
Solution Approach 1:
The patent merges the verification environments by implementing a unified co-simulator that handles both functional and fault verification. The system uses a single event queue, shared circuit model, and common control logic, eliminating the complexity of maintaining separate verification infrastructures while preserving the completeness of both verification types.
3Measurement precision
If manual fault simulation processes are used, then detailed fault analysis can be performed, but the processes are prone to errors and cannot accommodate changes in fault behavior effectively
Solution Approach 1:
The co-simulator implements automated feedback mechanisms that continuously monitor circuit state and fault conditions during simulation. The system automatically detects fault propagation, updates simulation parameters, and adjusts verification sequences based on real-time circuit behavior, eliminating manual intervention errors while maintaining precise fault analysis.
Solution Approach 2:
The simulation process is made dynamic and adaptive through automated fault injection and propagation tracking. The co-simulator can dynamically insert faults at any simulation point, automatically trace their propagation through the circuit, and adjust verification based on observed fault behavior, enabling effective accommodation of changing fault conditions.
4Reliability
If redundant calculations are performed in separate functional and fault verifications, then comprehensive coverage is achieved, but computational resources and workload increase
Solution Approach 1:
The patent eliminates redundant calculations by merging functional verification and fault simulation into a single concurrent process. The co-simulator shares the event queue, circuit evaluation logic, and result processing infrastructure between both verification types, ensuring that each circuit element is evaluated only once even though both verification objectives are met.
Data Source
AI summary
Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is initiated using the simulation data. A first machine region is identified during the functional simulation as associated with at least a first fault of the plurality of faults. A functional simulation of the first machine region is performed, and a divergence point associated with the first fault is identified. A fault simulation for the first fault is performed using the functional simulation of the first machine region and the divergence point.