Concurrent Fin and Gate Cut Etch for FinFET Fabrication
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Solution Overview
Problem
The existing methods for fabricating FinFET semiconductor devices require separate multilayer patterning stacks and lithography processes for fin and gate cut processes, complicating the process flow and increasing fabrication time.
Innovation Solution
Concurrent fin and gate cut processes are performed using a single mask layer with defined openings for both fin and gate cut cavities, allowing for the simultaneous formation of insulating material in these cavities, thereby reducing the complexity and time required for semiconductor device fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate multilayer patterning stacks and lithography processes are used for fin and gate cut processes, then manufacturing precision can be maintained, but device complexity and fabrication time increase
Solution Approach 1:
The patent combines the fin cut and gate cut processes into a single concurrent operation using a unified mask layer. The mask layer contains both fin cut openings and gate cut openings, allowing simultaneous patterning of both structures in one lithography and etch cycle, thereby reducing process flow complexity while maintaining cut cavity definition accuracy
Solution Approach 2:
The unified mask layer serves multiple functions: it defines both fin cut openings and gate cut openings, acts as a single patterning template for both structures, and enables concurrent etching of fins and gate structures. This multi-functionality eliminates the need for separate mask layers and lithography processes
2Manufacturing precision
If separate multilayer patterning stacks and lithography processes are used for fin and gate cut processes, then manufacturing precision can be maintained, but fabrication time increases
Solution Approach 1:
The concurrent fin and gate cut processes enable continuous fabrication without interruption between separate patterning steps. The single mask layer allows simultaneous etching of both fin and gate structures in one continuous process cycle, eliminating idle time and sequential waiting periods while maintaining precise cavity definition
Solution Approach 2:
By merging fin cut and gate cut into a single concurrent process using one mask layer, the patent reduces the total number of lithography and etch cycles required, thereby shortening fabrication time while preserving the precision needed for accurate cut cavity formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach shortens the process flow, increases throughput, and reduces costs by using a single hard mask for both fin and gate cut processes, while ensuring accurate definition of cut cavities for further device fabrication steps.
Implementation Method 1
A first etch process is performed to remove a first portion of the cap layer exposed by the gate cut opening to expose a second portion of a first gate structure of the plurality of gate structures
Data Source
AI summary
A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.