Concurrent FinFET Cut Etch Using Single Patterning Layer
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Solution Overview
Problem
The existing methods for fabricating FinFET semiconductor devices require separate multilayer patterning stacks and lithography processes for diffusion break, gate, and source/drain contact cut processes, complicating the process flow and increasing fabrication time.
Innovation Solution
A method for performing concurrent diffusion break, gate, and source/drain contact cut etch processes using a single patterning layer, which involves forming a semiconductor device with sacrificial gate structures, dielectric materials, and patterning layers to define recesses and cut structures, thereby simplifying the process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate multilayer patterning stacks and lithography processes are used for diffusion break, gate, and source/drain contact cut processes, then each process can be performed with dedicated precision, but the process flow complexity and fabrication time increase
Solution Approach 1:
The patent combines three separate patterning processes (diffusion break cut, gate cut, and source/drain contact cut) into a single concurrent etch process using one patterning layer. The patterning layer contains multiple openings that define all three cut features simultaneously, eliminating the need for separate multilayer patterning stacks and reducing process flow complexity while maintaining cut precision through unified process control
Solution Approach 2:
The single patterning layer serves multiple functions by defining diffusion break openings, gate cut openings, and source/drain contact cut openings all in one structure. This multi-functional patterning layer replaces three separate dedicated patterning layers, simplifying the overall fabrication process while maintaining the precision required for each specific cut type
2Manufacturing precision
If separate multilayer patterning stacks and lithography processes are used for diffusion break, gate, and source/drain contact cut processes, then each process can be independently optimized, but the fabrication time increases
Solution Approach 1:
The patent implements continuous useful action by performing all three cut processes (diffusion break, gate, and source/drain contact cuts) in a single continuous etch step rather than three separate sequential steps. The etch process continues through all features defined in the patterning layer simultaneously, eliminating idle time between processes and reducing total fabrication time while maintaining process control through unified parameters
Solution Approach 2:
By merging three separate lithography and etch processes into one concurrent process using a single patterning layer, the patent reduces the total number of process cycles. The single patterning step followed by a single etch step replaces three separate patterning and etching sequences, significantly reducing fabrication time while maintaining the ability to control each cut type through the unified process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and time required for fabrication by integrating the CT, DB, and TS cut processes into a single patterning layer, enhancing throughput and reducing costs.
Implementation Method 1
concurrent diffusion break, gate and source/drain contact cut etch processes
Data Source
AI summary
A device is formed including fins formed above a substrate, an isolation structure between the fins, a plurality of structures defining gate cavities, and a first dielectric material positioned between the structures. A patterning layer above the first dielectric material and in the gate cavities has a first opening positioned above a first gate cavity exposing a portion of the isolation structure and defining a first recess, a second opening above a second gate cavity exposing a first portion of the fins, and a third opening above a first portion of a source/drain region in the fins to expose the first dielectric material. Using the patterning layer, a second recess is formed in the substrate and a third recess is defined in the first dielectric material. A second dielectric material is formed in the recesses to define a gate cut structure, a diffusion break structure, and a contact cut structure.