Concurrent Gate Sizing and Repeater Insertion for ASIC Timing
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Solution Overview
Problem
Existing methods for gate sizing and repeater insertion in circuit design often result in sub-optimal timing and power performance due to sequential application and failure to consider conflicts in size requirements across interacting timing paths, leading to inefficiencies and oscillations in gate sizing algorithms.
Innovation Solution
A concurrent method for gate sizing and repeater insertion that assigns gates to levels based on logical connections, identifies coupled gates, generates and propagates repeater insertion solutions, and iteratively adjusts gate sizes to minimize cost and timing violations, using a dynamic programming approach to address conflicts and optimize both gate and repeater sizing simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate sizing and repeater insertion are applied sequentially, then the design process is simpler and easier to implement, but the timing and power performance becomes sub-optimal
Solution Approach 1:
The patent merges gate sizing and repeater insertion into a unified concurrent optimization framework. The algorithm simultaneously determines optimal gate sizes and repeater insertion locations by formulating a joint cost function that considers both gate sizing costs and repeater insertion costs, along with their interacting timing effects. This integration eliminates the sub-optimal results caused by sequential application while maintaining computational tractability through dynamic programming.
2Reliability
If concurrent gate sizing and repeater insertion are implemented, then timing and power performance is optimized, but the computational complexity increases
Solution Approach 1:
The patent segments the circuit into levels based on logical connections and processes gates level-by-level using dynamic programming. By dividing the concurrent optimization problem into manageable stages (levelization) and solving each stage sequentially with optimal substructure properties, the algorithm reduces computational complexity from exponential to polynomial time, making the concurrent approach practically implementable.
Solution Approach 2:
The patent employs dynamic programming where the cost function and timing calculations are updated dynamically as gates are processed level-by-level. The algorithm maintains and updates optimal costs and timing slacks incrementally, allowing efficient re-evaluation when gate sizes or repeater configurations change, thereby managing computational complexity through adaptive reuse of previous calculations.
3Ease of manufacture
If traditional sequential methods are used, then the implementation is straightforward, but conflicts in size requirements across interacting timing paths are not resolved, leading to oscillations
Solution Approach 1:
The patent combines gate sizing and repeater insertion into a unified concurrent optimization that resolves size requirement conflicts across interacting timing paths. By simultaneously considering all timing paths and their interactions in a single optimization framework with a comprehensive cost function, the algorithm eliminates the oscillations that arise from sequential methods where gate sizing and repeater insertion repeatedly adjust in response to each other's changes.
Solution Approach 2:
The patent incorporates feedback mechanisms where the timing slacks and cost functions are continuously updated based on the current gate sizes and repeater configurations. The algorithm uses this feedback to make coordinated adjustments that converge to a stable optimal solution, preventing the oscillations that occur when methods are applied sequentially without considering their mutual interactions.
Data Source
AI summary
Techniques for circuit concurrent gate sizing and repeater insertion considering the issue of size conflicts are described herein. Certain of these techniques can be directed to coupled gates within levels of a levelized circuit falling within a coupling window defined by a minimum slack gate and adjacent gates coupled to the minimum slack gate with an adjacency parameter less than a predefined adjacency limit.