Concurrent Protocol Header Writing for Wireless Packet Processing
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Solution Overview
Problem
Current methods for protocol header processing in packet-based communications networks are inefficient, particularly for battery-powered wireless communications devices, as they result in long delays and cannot handle high-speed, high-bandwidth data traffic effectively, and existing solutions like sequential processing and fixed function devices struggle to update header fields and operate at desired speeds.
Innovation Solution
A method and apparatus that involves decoding packets and concurrently writing protocol headers to both a packet buffer memory and respective protocol stack layer memories for immediate processing, using a direct memory access (DMA) device to facilitate simultaneous processing across protocol stack layers, allowing for direct access and processing of headers without sequential dependency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential processing approach is used for protocol headers, then processing order is maintained and system stability is improved, but processing time increases and productivity decreases
Solution Approach 1:
The patent segments the protocol header processing into multiple independent parallel processing paths, where each path handles a specific protocol layer or header field simultaneously. This allows the system to maintain processing integrity through structured segmentation while achieving speedup through parallel execution of these segments.
Solution Approach 2:
The patent implements preliminary action by pre-fetching and pre-processing protocol header data into dedicated buffer memory before the main processing sequence begins. This preparation phase allows subsequent processing stages to operate concurrently without waiting for sequential data retrieval, thereby reducing overall processing time while maintaining order.
2Productivity
If fixed function devices are used for header processing, then processing speed is improved, but adaptability to update header fields decreases
Solution Approach 1:
The patent employs dynamic processing elements that can adapt their behavior based on the specific protocol and header requirements. The system includes configurable processing units that can be dynamically programmed to handle different protocol stacks and header formats, providing both high-speed processing and adaptability to update header fields as needed.
Solution Approach 2:
The patent introduces an intermediary layer between the fixed function processing units and the variable protocol requirements. This intermediary includes programmable logic and control structures that translate dynamic protocol requirements into fixed function operations, enabling both speed and adaptability.
3Adaptability or versatility
If general purpose CPU is used for processing, then versatility is improved, but processing speed for high bandwidth traffic decreases
Solution Approach 1:
The patent replaces general-purpose CPU mechanical processing with specialized hardware acceleration units and dedicated logic circuits for protocol header processing. This substitution maintains versatility through programmable control while achieving the high-speed performance needed for high bandwidth traffic by eliminating the overhead of general-purpose instruction execution.
4Stability of the object's composition
If protocol headers are written sequentially to packet buffer memory, then memory access order is maintained, but processing time increases
Solution Approach 1:
The patent transitions from sequential one-dimensional memory access to multi-dimensional parallel memory access by organizing buffer memory into multiple independent access paths. Each processing unit can simultaneously write to or read from different memory locations or memory banks, maintaining logical access order while physically executing operations in parallel to reduce processing delay.
Data Source
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AI summary
A method is provided for processing a packet (300) at an egress end user node (110). The method includes a decoding step and a concurrent writing step. The concurrent writing step is performed subsequent to the decoding step. The decoding step involves decoding a packet having a plurality of headers (306-314). The concurrent writing step involves concurrently writing each of the headers (306-314) to a packet buffer memory (122) and a respective protocol stack layer memory (126-134). More specifically, a MAC layer protocol header (306) is concurrently written to the packet buffer memory and a MAC layer memory (126). An LLC layer protocol header (308) is concurrently written the packet buffer memory and an LLC layer memory (128). A network layer protocol header (310) is concurrently written to the packet buffer memory and a network layer memory (130), and so on.