Concurrent Inter-Tier Connections for 3D IC Voltage Drop
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In three-dimensional integrated circuits, the power and ground source density is restricted by packaging design rules and routing congestion, leading to significant voltage drop issues across different tiers, which adversely impact performance, power, and area (PPA) efficiency.
Innovation Solution
The method involves generating a 3D circuit design and providing concurrent inter-tier connections for both power/ground and signal networks, allowing for pre-assignment of connections to power-hungry blocks and post-assignment of spare connections to power grids, thereby improving voltage drop without incurring signal routing penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of power supply sources and inter-tier connections is increased to reduce voltage drop, then voltage drop is reduced, but power and ground source density is restricted by packaging design rules and routing congestion
Solution Approach 1:
The patent merges the coupling of inter-tier connections for power/ground networks and signal networks into a single concurrent process. This integration allows shared routing resources to be efficiently allocated, reducing overall routing congestion while maintaining sufficient power supply density to prevent voltage drop issues.
Solution Approach 2:
The patent performs pre-assignment of inter-tier connections to power-hungry blocks during the design phase, before final routing is completed. This preliminary action ensures that power supply sources are strategically positioned to prevent voltage drop, while the concurrent coupling process later optimizes the overall routing efficiency.
2Reliability
If more inter-tier connections are provided for power and ground, then voltage drop is reduced, but routing resources are occupied adversely impacting performance, power, and area
Solution Approach 1:
The patent combines the routing of power/ground connections and signal connections into a single concurrent process, allowing shared routing resources to serve multiple purposes. This merging reduces the total routing resources occupied while ensuring adequate power supply for voltage drop prevention, thereby maintaining PPA efficiency.
Solution Approach 2:
The patent enables inter-tier connections to serve dual functions: providing power/ground supply to prevent voltage drop and carrying signal traffic. This multi-functionality maximizes the utilization of routing resources, reducing the need for dedicated power routing and improving overall PPA efficiency.
3Reliability
If inter-tier connections are assigned to power networks, then voltage drop is reduced, but signal routing flexibility is reduced due to routing congestion
Solution Approach 1:
The patent performs preliminary assignment of inter-tier connections to power-hungry blocks, identifying critical power supply needs before final routing decisions. This allows power/ground connections to be established in advance where most needed, while leaving other inter-tier connections available for flexible signal routing.
Solution Approach 2:
The patent implements a dynamic, concurrent coupling process that adaptively allocates inter-tier connections based on real-time routing needs. Power/ground connections are established where voltage drop risks exist, while signal routing flexibility is maintained through dynamic resource allocation during the concurrent process.
Data Source
AI summary
According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.