Concurrent Interconnection Diagnostics for Functional Verification Systems
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Solution Overview
Problem
Current hardware-based functional verification systems face challenges in concurrent interconnection diagnostics, leading to disruptions and inefficiencies during the verification process, as they require taking emulation boards offline for testing, which affects the implementation of hardware designs and introduces errors.
Innovation Solution
The implementation of methods and systems that enable concurrent interconnection diagnostics by using error correction code check bits, test patterns, and multiplexers to test interconnections while the system runs a hardware design, allowing for continuous operation and reducing the need for extensive re-location of hardware designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnection testing is performed using traditional methods, then interconnection failures can be detected, but the emulation board must be taken offline causing disruption to hardware design verification
Solution Approach 1:
The patent implements concurrent interconnection diagnostics that allow testing to occur continuously alongside hardware design verification. The system maintains continuous operation by performing diagnostics during idle periods or using dedicated test resources, eliminating the need to stop production verification work.
Solution Approach 2:
The patent segments the emulation board resources into separate test domains and production domains. By dividing the system into independent functional segments, testing can proceed in isolated regions without affecting the overall verification process, allowing concurrent operation of test and production activities.
2Measurement precision
If emulation boards are taken offline for interconnection testing, then diagnostic accuracy is improved, but the time required for verification is increased
Solution Approach 1:
The patent implements periodic diagnostic testing where interconnection health is assessed at regular intervals during verification operations. This periodic approach maintains diagnostic accuracy through repeated measurements while minimizing time loss by using brief, scheduled test windows rather than extended offline periods.
Solution Approach 2:
The patent performs preliminary interconnection diagnostics before major verification tasks begin, establishing a baseline health status. This preliminary action prevents unexpected failures during critical verification phases and allows for proactive maintenance scheduling that minimizes disruption to the verification timeline.
3Difficulty of detecting and measuring
If dedicated test logic is implemented on emulation chips, then interconnection testing capability is enhanced, but device complexity increases
Solution Approach 1:
The patent implements multi-functional test logic that serves both interconnection diagnostics and hardware verification functions. The same emulation chip resources are utilized for both production verification and diagnostic testing, eliminating the need for entirely separate dedicated test hardware and reducing overall system complexity.
Solution Approach 2:
The patent enables emulation chips to perform self-diagnostics where the chips monitor and test their own interconnections using built-in diagnostic capabilities. This self-service approach enhances testing capability without requiring external test equipment or significantly increasing chip complexity, as the chips use their own resources for self-verification.
Data Source
AI summary
Methods and systems for concurrent diagnostics in a functional verification system are disclosed and claimed herein. The methods and systems enable testing the interconnections of a functional verification system while the system implements a hardware design. In one embodiment, a first emulation chip of the functional verification system generates an encoded data word comprising a data word and error correction code (ECC) check bits. The ECC check bits enable a second emulation chip receiving the encoded word to determine whether the data word was received without error. In another embodiment, test patters may be transmitted along the unused interconnections while the functional verification system implements a hardware design in other interconnections. In another embodiment, a dedicated pattern generator generates test patterns to transmit across the interconnection. During clock cycles in which the interconnection is not used to implement the hardware design, a multiplexer transmits the test pattern across the interconnection.