Concurrent L1 and L2 Cache Flushing via Microcode Segmentation
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Solution Overview
Problem
Conventional cache flushing methods in processor-based systems are sequential, leading to significant latency and delay when performed frequently, as they require approximately 270 K clock cycles for flushing both L1 and L2 caches, which can cause substantial overhead and inefficiency.
Innovation Solution
Implementing a cache controller to enable concurrent flushing of L1 and L2 caches, allowing both caches to be flushed simultaneously, reducing latency and improving efficiency by coordinating the flushing process through microcode and hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sequential flushing method is used for L1 and L2 caches, then cache flushing can be performed with simple control logic, but the latency and time required for flushing increases significantly
Solution Approach 1:
The patent segments the cache flushing operation into independent L1 and L2 cache flushing tasks that can execute concurrently. The segmentation is achieved by dividing the flushing control into separate microcode sequences (first microcode sequence for L1, second microcode sequence for L2) that run in parallel, thereby reducing total flush time while maintaining simple control logic for each segment
Solution Approach 2:
The patent transitions from sequential time-based flushing to concurrent parallel flushing by adding a temporal dimension. The flushing operations that previously executed one after another in a single time stream now execute simultaneously across multiple time streams, reducing the total time required while maintaining operational simplicity through structured microcode sequences
2Device complexity
If sequential flushing method is used for L1 and L2 caches, then hardware complexity remains low, but the number of clock cycles required increases to approximately 270 K
Solution Approach 1:
The patent merges the L1 and L2 cache flushing operations into a single concurrent execution framework. By combining both flushing tasks into parallel microcode sequences that execute simultaneously, the system achieves higher productivity without requiring separate hardware flushing units, thus avoiding increased hardware complexity
Solution Approach 2:
The patent implements a universal flushing mechanism that handles both L1 and L2 caches through a single integrated approach. The same hardware infrastructure and control framework are used to manage both cache levels concurrently, eliminating the need for dedicated separate flushing hardware and maintaining low device complexity while improving flushing speed
3Reliability
If frequent cache flushing is performed using sequential method, then data consistency is maintained, but substantial overhead and inefficiency occur
Solution Approach 1:
The patent segments the flushing process into independent concurrent tasks for L1 and L2 caches, allowing both to be flushed simultaneously. This segmentation maintains data consistency by ensuring both caches are properly flushed while reducing the total time overhead by a factor of approximately 8 compared to sequential flushing
Solution Approach 2:
The patent implements continuous concurrent flushing operations that proceed without interruption. By maintaining continuous useful action through parallel execution of L1 and L2 flushes, the system achieves both data consistency and improved efficiency, eliminating the idle waiting time present in sequential methods
Data Source
AI summary
The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a multi-level cache. Each first cache is smaller and at a lower level in the multi-level cache than the second level cache.