Concurrent Limit Address Check in PCI Express Switches
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Solution Overview
Problem
Conventional PCI Express switches face challenges in accommodating a large number of external devices due to the need for an exponentially increasing number of comparators and registers, leading to increased latency and chip space consumption.
Innovation Solution
A method and device for concurrent limit address checking in a PCI Express serial switch, which uses a multiplexer to select content from base address registers, comparators to match the target address with base and limit addresses, and inhibits packet transmission if the target address exceeds the limit address, allowing for rapid address searching without excessive hardware usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of comparators is increased to accommodate more external devices, then the switch can support more ports, but the chip space consumption and power consumption increase exponentially
Solution Approach 1:
The patent segments the address matching function into two separate comparator stages: a first comparator that performs initial address range checking, and a second comparator that performs limit address validation. This segmentation allows the system to handle more ports without requiring a single large comparator array, thus reducing overall chip space consumption while maintaining adaptability.
Solution Approach 2:
The patent introduces a temporal dimension to the address checking process by performing limit address checking in a second stage after initial matching. This multi-stage approach transforms the spatial complexity (all comparators needed simultaneously) into a temporal process (comparators used sequentially), enabling support for more ports without exponential growth in comparator count.
2Device complexity
If conventional address checking is performed sequentially, then hardware resources are reduced, but system latency increases due to non-concurrent limit address checking
Solution Approach 1:
The patent performs preliminary address range checking in the first comparator stage to identify candidate addresses before performing the more detailed limit address validation in the second stage. This preliminary filtering reduces the number of addresses that require full validation, thereby reducing overall hardware resources while maintaining low latency through the efficient two-stage process.
Solution Approach 2:
The patent resolves the latency-hardware tradeoff by introducing a temporal dimension with two sequential checking stages. The first stage quickly filters addresses using base address comparison, and the second stage validates limits only for matching addresses. This transforms the problem from requiring all comparators to operate simultaneously (high hardware) or sequentially (high latency) to a balanced two-stage approach that optimizes both dimensions.
Data Source
AI summary
A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a multiplexer that is enabled to select content from a base address register in an array of base address registers, a comparator enabled compare a base address in the content with a target address from a packet, and a comparator enabled to concurrently compare a limit address in the content with the target address and the output of the limit address comparator. The method includes receiving the target address, locating a matching base address in an array of base address registers, concurrently comparing the target address with a limit address associated with the matching base address, and indicating if said target address is not valid.