Concurrent Memory and Logic Gate Fabrication
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Solution Overview
Problem
Existing non-volatile memory cell arrays face challenges in forming logic devices with different operational thresholds on the same semiconductor chip due to adverse processing effects on previously fabricated logic devices and the limitations of polysilicon conductive gates, especially as device geometries shrink, requiring new gate materials for improved conductivity and performance.
Innovation Solution
A method for simultaneously forming memory cells, low voltage logic devices, and high voltage logic devices on the same semiconductor substrate using shared processing steps, with memory cells having a floating gate, control gate, and word line gate, and logic devices with channel regions and gates insulated by high K materials, reducing the need for multiple photolithographic masks and thermal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon conductive gates are used in memory cells, then the memory cells can be formed with conventional processing, but the conductivity is insufficient as device geometries shrink
Solution Approach 1:
The patent changes the material parameter from polysilicon to metal gate materials (such as tungsten, titanium nitride, or other conductive metals), fundamentally altering the electrical conductivity parameter to meet the requirements of scaled device geometries while maintaining compatibility with modified conventional processing steps
Solution Approach 2:
The patent employs composite gate structures that may include multiple layers (such as titanium nitride over tungsten, or other metal combinations) to achieve both the required conductivity and appropriate work function characteristics for different device types on the same chip
2Reliability
If logic devices are fabricated before memory cells, then logic devices can be formed first, but subsequent memory cell processing adversely affects the logic devices
Solution Approach 1:
The patent merges the fabrication processes for logic devices and memory cells into a single concurrent process sequence, where both device types are formed simultaneously using shared processing steps (such as joint gate formation, joint doping steps, and shared etch processes), eliminating the need for separate fabrication sequences and the adverse effects that result from sequential processing
Solution Approach 2:
The patent creates universal processing steps that serve both logic device and memory cell fabrication simultaneously, such as a single gate patterning step that defines gates for both device types, and shared dielectric layer formations that benefit both device structures, thereby reducing overall process complexity
3Adaptability or versatility
If multiple photolithographic masks and thermal processes are used to form different device types, then device differentiation is achieved, but processing complexity and unwanted effects increase
Solution Approach 1:
The patent applies local quality by using selective doping regions, locally varied dielectric thicknesses, and spatially selective material depositions within the concurrent fabrication process to differentiate between logic and memory devices, achieving device-specific characteristics without requiring separate global processing sequences
Solution Approach 2:
The patent incorporates preliminary actions such as pre-defined doping profiles, pre-formed dielectric layers with varying thicknesses, and pre-patterned sacrificial structures that enable subsequent selective processing steps to differentiate device types with fewer additional masks and processes
Data Source
Figure 1A~3A
Figure 1B~3B
Figure 1C~3C
AI summary
A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.