Concurrent Memory Plane Programming with Independent Voltage Biasing
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Solution Overview
Problem
High-density non-volatile memory structures, such as multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC) memory devices face slower programming speeds and higher precision requirements due to tightened tolerances between voltage ranges, limiting their performance compared to single-level cell (SLC) devices.
Innovation Solution
A method and system for concurrently programming multiple memory planes and blocks with independent voltage biasing, allowing for asynchronous or synchronous operations across different memory structure types, including SLC, MLC, TLC, and QLC, using a global or multiple voltage bias sources to improve programming efficiency and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) memory structures are used to increase storage density, then storage capacity is improved, but programming speed deteriorates due to tighter tolerances between voltage ranges
Solution Approach 1:
The memory system is divided into multiple independent memory planes, each capable of being programmed separately. This segmentation allows different planes to be programmed in parallel, compensating for the slower programming speed of high-density cells by increasing the number of simultaneous programming operations across multiple planes
Solution Approach 2:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically-stacked memory planes. This vertical stacking enables multiple memory planes to be stacked above a common substrate, allowing concurrent programming operations across multiple planes while maintaining high storage density
2Quantity of substance
If multi-level cell (MLC), triple-level cell (TLC), or quad-level cell (QLC) memory structures are used to increase storage density, then storage capacity is improved, but manufacturing precision requirements worsen due to tighter voltage range tolerances
Solution Approach 1:
Each memory plane is equipped with independent voltage bias sources that can provide customized voltage profiles tailored to the specific requirements of that plane. This local control allows each plane to operate within its optimal voltage ranges, accommodating variations in manufacturing tolerances across different planes while maintaining high storage density
3Device complexity
If sequential programming approaches are used in memory structures, then device complexity is reduced, but productivity deteriorates due to slower overall programming performance
Solution Approach 1:
The memory controller is designed to universally manage multiple memory planes with different structure types (SLC, MLC, TLC, QLC) through a unified control architecture. This multi-functional controller can issue programming commands to multiple planes simultaneously, maintaining operational simplicity while achieving high productivity through parallel processing
Solution Approach 2:
The system enables continuous programming operations across multiple memory planes by eliminating idle time between programming cycles. While one plane is being programmed, other planes can simultaneously undergo programming or verification operations, ensuring that the system continuously performs useful work without sequential waiting periods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the performance of memory devices by enabling concurrent and independent operations across multiple memory planes and blocks, improving programming speed and efficiency while accommodating different memory types, thus overcoming the limitations of traditional sequential approaches.
Implementation Method 1
using the voltage bias source, concurrently applying the memory operation to the respective selected memory blocks and the respective selected word lines
Data Source
AI summary
Method for performing a memory operation with respect to a memory structure having “N”-number of planes, each plane comprising “M”-number of blocks and “X”-number of word lines arranged in a serial order, and electrically connected with each plane are: a voltage bias source, an electronic switching component, and row decoder, the method comprising: with respect to each plane, selecting a block and a word line for application of the operation, wherein the operation has not been applied to the selected block and word line, the selected block of one plane is located in a different block group from the selected block of another plane, and the selected word line of one plane is in a different position within the serial order from a position of the selected word line of another plane; and using the voltage bias source, concurrently applying the operation to the selected blocks and selected word lines.