Concurrent Memory Operations for Read Preemption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory systems like NAND non-volatile memory, simultaneous read and write operations are often restricted, with read operations completing much faster than write operations, leading to performance degradation due to the need to wait for write operations to finish before proceeding with read operations.
Innovation Solution
Implementing a memory interface with concurrent memory operations that allow a write operation to be suspended and resumed concurrently with the transfer of read data, reducing delays and improving system performance by enabling quicker resumption of write operations and faster execution of read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system waits for write operation completion before proceeding with read operation, then write operation integrity is maintained, but system performance deteriorates due to idle waiting time
Solution Approach 1:
The system performs preliminary suspension of the write operation when a read operation is requested, allowing the read operation to proceed without waiting for write completion. The write operation is then resumed after the read operation completes, maintaining data integrity while improving performance.
Solution Approach 2:
The system dynamically adjusts the execution state of write operations based on read operation requirements. Write operations can be suspended, resumed, and re-suspended multiple times during their execution, allowing flexible coordination between read and write operations to optimize system performance.
2Speed
If read operation preempts ongoing write operation, then read operation speed is maintained, but write operation completion time increases
Solution Approach 1:
The write operation is executed in periodic segments that can be interrupted and resumed. When a read operation preempts the write operation, the write operation pauses and resumes later, creating a periodic execution pattern that allows both operations to progress without excessive delays.
3Productivity
If multiple suspend and resume commands are issued for write operation, then read operation bandwidth is improved, but control logic complexity increases
Solution Approach 1:
The memory interface automatically manages the suspension and resumption of write operations based on read operation requests. The control logic monitors the state of write operations and autonomously issues suspend and resume commands without requiring complex external coordination, simplifying the overall control architecture.
Data Source
AI summary
A non-volatile memory interface employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation. Memory control logic of the memory interface is configured to issue to the write operation suspend logic, a write operation resume command. The transaction control logic may be further configured to automatically suspend performing of a write operation in response to receipt of a read command. The transaction control logic may also be configured to automatically resume a previously suspended write operation in response to completion of a preemptive read operation by the memory.