Memory Block Operations for Concurrent Activation and Refresh
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Solution Overview
Problem
Volatile memory devices like DRAM face challenges in maintaining data integrity due to leakage currents and disturbances from adjacent cells, especially with increasing integration, leading to inefficient refresh operations that affect access times and data retention.
Innovation Solution
A memory device and system that performs simultaneous activation and refresh operations on different blocks within a bank array, utilizing separate bit line sensing areas and controlled by a memory controller to optimize refresh timing and reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operation is performed separately from activation operation, then data integrity is maintained, but access latency increases and productivity decreases
Solution Approach 1:
The patent combines refresh operation and activation operation into a single unified operation. The memory device performs both operations simultaneously by activating a target row for data access while also refreshing a different row, thereby maintaining data integrity without increasing access latency. This merging of operations allows the memory system to achieve both reliability and productivity improvements.
Solution Approach 2:
The patent enables continuous useful action by performing refresh operations during the activation operation timeframe. Instead of separating refresh and activation into distinct time periods, the system continuously performs both operations overlapping in time, ensuring that refresh does not interrupt data access and maintaining high productivity while preserving data integrity.
2Productivity
If refresh operation is performed concurrently with activation operation, then productivity improves, but device complexity increases
Solution Approach 1:
The patent segments the memory device into multiple independent blocks, where each block can independently perform activation and refresh operations. This segmentation allows the control logic to manage concurrent operations more easily by treating each block as an independent unit, thereby reducing the overall complexity burden while maintaining high productivity through parallel operations.
Solution Approach 2:
The patent introduces an intermediary mechanism (the unified activation-refresh command interface) that simplifies the control of concurrent operations. Instead of requiring separate complex control logic for activation and refresh, the system uses a unified command structure that automatically coordinates both operations, reducing device complexity while enabling concurrent execution for improved productivity.
3Device complexity
If activation operation and refresh operation share the same bit line sensing area, then device complexity is reduced, but data integrity deteriorates due to interference
Solution Approach 1:
The patent segments the bit line sensing area into block-specific sensing regions, where each block has its own dedicated sensing area. This segmentation prevents interference between activation and refresh operations by ensuring that operations in different blocks do not share sensing resources, thereby maintaining data integrity while managing device complexity through modular organization.
Solution Approach 2:
The patent applies local quality by providing dedicated bit line sensing areas for different blocks, allowing each block to have optimized sensing resources tailored to its specific operations. This local specialization ensures that activation and refresh operations in different blocks do not interfere with each other, maintaining high data integrity while the overall device structure remains organized and manageable.
Data Source
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AI summary
A memory device and an operating method of the memory device are provided. The operating method comprises receiving an activation-refresh command from a memory controller, decoding a target address and an internal command from the activation-refresh command, and performing an activation operation based on the internal command for the target address and performing a refresh operation on at least one block to which the target address does not belong.