Concurrent Multi-Bit Adder Using Associative Memory
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Solution Overview
Problem
Ripple carry adders become slow and inefficient when performing large multi-bit additions due to serial computation complexity of O(N), where each step depends on the completion of previous steps and requires specialized hardware for carry look-ahead calculations.
Innovation Solution
A multi-bit concurrent adder system utilizing a non-destructive associative memory array with sections storing bits of operands in rows and columns, performing parallel Boolean operations and predicting carry values to improve computation efficiency by splitting operands into groups and calculating carry outs in parallel using predictor and selector components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ripple carry adder is used for multi-bit addition, then the circuit structure is simple and easy to implement, but the computation speed becomes slow due to serial dependency of O(N) complexity
Solution Approach 1:
The patent segments the multi-bit addition process into independent parallel operations by organizing bits into columns where each column processes a specific bit position simultaneously. The memory array is divided into multiple columns, each handling a specific bit position of multiple operand pairs, allowing concurrent computation across all bit positions rather than sequential propagation.
Solution Approach 2:
The patent transitions from the traditional horizontal ripple carry approach to a vertical column-based organization in the memory array. By stacking memory cells in columns where each column represents a bit position, the carry propagation occurs vertically through the memory structure rather than horizontally through sequential logic gates, enabling parallel processing of multiple bit positions.
2Speed
If carry look-ahead logic is added to improve computation speed, then the speed increases, but the device complexity and hardware requirements increase significantly
Solution Approach 1:
The patent makes the memory array perform multiple functions: it stores the input operands and simultaneously performs the addition operation. The same memory structure that holds the data also generates the sum and carry outputs through in-place computation, eliminating the need for separate dedicated adder circuits and reducing overall hardware complexity.
Solution Approach 2:
The memory array performs the addition operation on the data already stored within it, without requiring external specialized adder hardware. The computation is self-contained within the memory structure, where the stored bits directly participate in the addition process and generate results that remain in the same array.
3Device complexity
If serial computation is used to reduce hardware complexity, then the device complexity is low, but the computation time increases due to sequential processing
Solution Approach 1:
The patent pre-organizes the operand bits into column structures within the memory array before computation begins. Each column is pre-configured with the corresponding bits from multiple operands at the same bit position, so that when addition is initiated, all columns can compute simultaneously without waiting for carry propagation from previous bit positions.
Data Source
AI summary
A method for an associative memory device includes performing in parallel multi-bit operations of P pairs of multi-bit operands stored in columns of a memory array, each pair is stored in a different column, each bit i of each multi-bit operands of each pair is stored in a row of a section i in the column and each operation occurs in its associated column. A system includes a non-destructive associative memory array with multiple sections, each section j includes cells arranged in rows and columns, to store a bit j from a first multi-bit number in a first row and a bit j from a second multi-bit number in a second row of a same column, and a concurrent adder to, in parallel, perform per-section operations in each section, that includes one or more Boolean operations between a plurality of bits stored in rows of the section.