Concurrent Non-Volatile Memory Testing in System-on-Chip
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Solution Overview
Problem
The testing of non-volatile memories, such as flash memories, in System-on-Chips is time-consuming due to their slow access times, contributing to increased production costs and overall test time.
Innovation Solution
A device and method that includes a processor, non-volatile memory, and a test controller, where the processor tests other circuit parts while the test controller tests the non-volatile memory concurrently, utilizing a built-in self-test controller to perform parallel testing during certain phases, thereby reducing overall test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential testing is used where the processor tests all circuit parts before testing the non-volatile memory, then the testing can be completed systematically, but the overall test time increases significantly
Solution Approach 1:
The testing system is segmented into two independent testing paths: one for the processor to test circuit parts and another for the test controller to test the non-volatile memory. This segmentation allows both tests to proceed simultaneously without interfering with each other, thereby reducing overall test time while maintaining systematic testing through separate test sequences.
Solution Approach 2:
The patent merges the processor-based circuit testing and the controller-based memory testing into a single integrated test flow that executes both tests in parallel. By combining these testing operations into one concurrent process rather than sequential steps, the system achieves faster overall testing while maintaining the reliability of both test components.
2Device complexity
If the processor tests the non-volatile memory sequentially after testing other circuit parts, then resource allocation is simple, but the test time contribution from memory testing becomes a significant portion of total test time
Solution Approach 1:
The test controller is designed with multi-functionality to handle both memory testing operations and coordinate with the processor's circuit testing. This universal test controller can independently manage memory test sequences while allowing the processor to simultaneously test other circuits, thereby increasing testing throughput without requiring multiple specialized testing devices that would increase system complexity.
Data Source
AI summary
Devices, systems and methods are provided which comprise testing of a non-volatile memory concurrently during at least a part of a testing of other system parts by a processor. In some examples, a device includes a processor, a non-volatile memory, a test controller, and at least one further circuit part. In a test mode, the processor is configured to test the at least one further circuit part, and wherein the test controller is configured to test the non-volatile memory concurrently with at least part of the testing of the at least one further circuit part.