Concurrent Multiple Page Read Memory Controller with Segmented Voltage Regulators
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Solution Overview
Problem
Memory devices face challenges in increasing read speeds without expanding the memory die footprint, as existing technologies are limited by the need for larger silicon real estate to support concurrent multiple page reads.
Innovation Solution
The implementation of a memory controller with first and second wordline control logic, including voltage regulators, allows for concurrent access to multiple pages of memory cells at different programming levels, using CMOS under the array techniques to maintain existing dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the size of memory die is increased to support concurrent multiple page reads, then data access rate is improved, but memory footprint increases
Solution Approach 1:
The memory controller is segmented into multiple independent wordline control logic units (first wordline control logic, second wordline control logic, etc.), each capable of independently controlling a separate page of memory cells. This segmentation enables parallel operation of multiple control units to read multiple pages concurrently without requiring additional silicon real estate beyond the controller logic.
Solution Approach 2:
The patent utilizes the time dimension by implementing pipelined operation where multiple pages are read in overlapping time periods. The memory controller processes multiple read requests concurrently by distributing them across different wordline control logic units operating in parallel, effectively increasing data access rate without expanding the physical memory array area.
2Adaptability or versatility
If multiple voltage regulators are added to support concurrent reads at different programming levels, then read capability is improved, but device complexity increases
Solution Approach 1:
The voltage regulation functionality is segmented and distributed across multiple independent wordline control logic units. Each control logic unit includes its own voltage regulator that can generate appropriate voltage levels for specific programming levels (e.g., SLC, MLC, TLC, QLC). This distributed architecture enables concurrent reads at different programming levels while maintaining manageable complexity through modular design.
Solution Approach 2:
Each wordline control logic unit is designed as a universal module capable of handling multiple programming levels (SLC, MLC, TLC, QLC) through its integrated voltage regulator. This multi-functional design allows the same control logic structure to serve multiple purposes across different memory cell types, reducing overall device complexity compared to having separate dedicated circuits for each programming level.
Data Source
AI summary
A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.