Concurrent Programming of Non-Volatile Memory Cells

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Solution Overview

Problem

Conventional methods for programming multiple cells in non-volatile memory devices require separate operations, increasing time and steps due to the need for verifying and writing temporary data copies, which hampers efficiency and performance.

Innovation Solution

The implementation of a system and method for concurrently programming multiple storage cells by applying a programming pulse to multiple word lines simultaneously, with a verification pulse to ensure correct programming, allowing for separate programming if necessary, and utilizing cell compaction operations to optimize data storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate programming operations are used for multiple cells, then programming accuracy and verification can be ensured, but programming time and operational steps increase

Engineering Contradiction:
Improveprogramming verification accuracyVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges multiple separate programming operations into a single concurrent programming operation. By applying programming pulses to multiple word lines simultaneously through a shared bit line, the system programs multiple cells in parallel, reducing total programming time while maintaining verification accuracy through subsequent verify operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary actions by temporarily writing data to multiple storage cells before final encoding. This preliminary writing phase allows concurrent programming of temporary copies, which are later verified and combined through cell compaction operations, thereby reducing overall encoding time while ensuring data accuracy.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If temporary data copies are written to multiple cells before MLC storage, then data redundancy and reliability improve, but the number of programming steps increases

Engineering Contradiction:
Improvedata redundancyVSAvoidnumber of programming steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple programming steps into concurrent operations. By using a shared bit line to program multiple word lines simultaneously, the system reduces the number of sequential programming steps while maintaining data redundancy through temporary copies in multiple cells, which are later consolidated via cell compaction.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If conventional separate programming methods are used, then programming precision can be maintained, but productivity and throughput decrease

Engineering Contradiction:
Improveprogramming precisionVSAvoidencoding throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent merges multiple programming operations into concurrent executions. By applying programming pulses to multiple word lines through a shared bit line simultaneously, the system maintains programming precision through verify operations while significantly increasing encoding throughput through parallel processing of multiple cells.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the operational parameters by transitioning from sequential to concurrent programming. This parameter change involves coordinating multiple word line selections and timing pulses to achieve parallel programming, thereby improving productivity while maintaining precision through subsequent verification steps.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11342028B2Concurrent programming of multiple cells for non-volatile memory devices
Publication Date: 2022.05.24 SANDISK TECHNOLOGIES LLC
  • US11342028B2 patent drawing
  • US11342028B2 patent drawing
  • US11342028B2 patent drawing

AI summary

Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.