Concurrent Read Control Circuit for Resistive Memory
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Solution Overview
Problem
Resistive memory devices face challenges in improving reading speed while reducing the likelihood of erroneous reads during concurrent operations, particularly due to fluctuations in current through word lines when multiple memory cells are read simultaneously.
Innovation Solution
The semiconductor storage device employs a control circuit that applies voltages to selected bit lines and word lines in a controlled manner, allowing for concurrent read operations with adjustable numbers of bit lines, and includes multiple read operations with varying bit line participation to minimize current fluctuations and erroneous reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If concurrent read operations are performed on multiple memory cells, then reading speed is improved, but current fluctuations through word lines increase causing erroneous reads
Solution Approach 1:
The patent segments the concurrent read operation into multiple stages, where bit lines are activated in different groups across stages. Instead of activating all bit lines simultaneously, the read operation is divided so that different subsets of bit lines are activated in sequence, reducing the number of memory cells read concurrently in each stage and thereby reducing current fluctuations on word lines.
Solution Approach 2:
The patent dynamically adjusts the number of bit lines activated in each stage based on the read operation requirements. The control circuit selectively activates different numbers of bit lines in different stages, optimizing the balance between reading speed and read accuracy. This dynamic adjustment allows the system to adapt the concurrent read capacity to minimize current fluctuations while maintaining high overall reading speed.
2Productivity
If more bit lines are activated concurrently, then more memory cells are read simultaneously improving speed, but current fluctuation increases leading to erroneous reads
Solution Approach 1:
The patent divides the set of bit lines into multiple groups that are activated in different stages. In each stage, only a subset of bit lines is activated, which limits the number of memory cells being read simultaneously and controls the current fluctuation on shared word lines. This segmentation maintains high read throughput by efficiently utilizing multiple bit lines while avoiding excessive current fluctuations.
Solution Approach 2:
The patent employs periodic activation of bit line groups across multiple stages. Rather than a single simultaneous activation of all bit lines, the system periodically activates different groups of bit lines in sequence, distributing the current load over time and reducing peak current fluctuations that would cause erroneous reads.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances reading speed while reducing the likelihood of erroneous reads by managing current fluctuations through controlled voltage application and staged read operations, ensuring accurate data retrieval in high-density memory cell arrays.
Implementation Method 1
the variable resistance element changes from a high resistance state to a low resistance state
Implementation Method 2
monitoring at a sense amplifier circuit the current flowing through the variable resistance element (specifically, detecting a change in voltage of a bit line)
Data Source
AI summary
A semiconductor storage device includes a memory cell array including memory cells arranged at respective intersections between first wirings and second wirings. Each of the memory cells includes a rectifier element and a variable resistance element connected in series. A control circuit is configured to apply a first voltage to a selected first wiring and a second voltage lower than the first voltage to a selected second wiring so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring. The control circuit performs a concurrent read operation to perform a read operation from plural memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently. It is possible to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation.