Concurrent Scheduler Synthesis for Multicore Architectures

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional scheduling technologies for parallel programming, especially for irregular algorithms, are limited in handling dynamic dependencies and complex scheduling requirements, leading to inefficiencies and increased complexity in programming.

Innovation Solution

A high-level language for generating scheduling specifications and synthesizing schedulers that allow for more sophisticated scheduling strategies without requiring explicit parallel code, using workset objects with extended poll methods and relaxed correctness conditions to enable efficient and flexible scheduling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional scheduling technologies are used for parallel programming, then implementation is simpler, but handling of dynamic dependencies and complex scheduling requirements is limited

Engineering Contradiction:
Improvescheduling strategy flexibilityVSAvoidprogramming complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a high-level scheduling specification language as an intermediary between the programmer and the complex scheduler implementation. This specification language allows programmers to express scheduling requirements (such as ordering constraints and resource dependencies) in a simple, declarative manner, while an automated synthesis tool translates these specifications into correct concurrent scheduler code, thus resolving the contradiction between scheduling flexibility and programming complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system employs automated synthesis tools that automatically generate scheduler implementations from high-level specifications. The synthesis process includes automatic verification of correctness properties and optimization of scheduler performance, eliminating the need for programmers to manually implement complex concurrent scheduling logic while ensuring correctness and adaptability.

Inventive Principle:
Principle #25Self-service

2Ease of operation

If explicit parallel code is written, then scheduling control is more precise, but programming complexity increases

Engineering Contradiction:
Improvescheduling controlVSAvoidcode complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent extracts the complex aspects of parallel programming (synchronization, ordering constraints, resource management) from the programmer's direct control and encapsulates them in a high-level specification language. Programmers only need to specify what scheduling constraints exist, while the synthesis tool automatically handles the complex implementation details of concurrent control, thus achieving precise scheduling control without increased code complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If fixed-function schedulers are used, then implementation is simpler, but performance for irregular algorithms is limited

Engineering Contradiction:
Improvealgorithm performanceVSAvoidscheduler complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent enables dynamic scheduling behavior by allowing the specification language to express runtime-dependent scheduling constraints and by generating schedulers that can adapt their behavior based on actual execution conditions. The synthesized schedulers can handle irregular algorithms effectively by translating high-level scheduling specifications into dynamic dispatch logic that responds to runtime dependencies and workload characteristics.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The synthesis tool can generate multiple scheduler variants with different parameters and optimization strategies based on the same high-level specification. This allows selection of scheduler implementations optimized for specific algorithm characteristics (such as irregular workloads), achieving high performance without manually implementing complex scheduler logic for each case.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8732712B2Synthesis of concurrent schedulers for multicore architectures
Publication Date: 2014.05.20 BOARD OF RGT THE UNIV OF TEXAS SYST
  • US8732712B2 patent drawing
  • US8732712B2 patent drawing
  • US8732712B2 patent drawing

AI summary

Systems and methods provide a high-level language for generation of a scheduling specification based on a scheduling policy, and synthesis of scheduler based on the scheduling specification. The systems and methods can permit the use of more sophisticated scheduling strategies than those afforded by conventional systems, without requiring the programmer to write explicitly parallel code. In certain embodiments, synthesis of the scheduler includes implementation of at least one rule related to the scheduling specification through definition of one or more workset objects that are concurrent, a workset object of the one or more workset objects having an addition method, a first poll method, and a second poll method. Such poll methods extend the operability of sequential poll methods. The one or more worksets satisfy a condition for correctness that is less stringent than conventional conditions for correctness.