Concurrent Software and Hardware Verification for SoC
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Solution Overview
Problem
Current circuit design verification processes are inefficient, particularly for large complex designs like SoC, due to slow software simulation and the need for complete software stacks to be completed before hardware verification can begin, prolonging the overall verification process and limiting early software development and hardware validation.
Innovation Solution
A system with a reconfigurable hardware modeling device and two computing units that allow concurrent execution of software programs and testbench models, generating stimuli for a hardware model through a communication interface, enabling simultaneous software and hardware verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software simulation is used for functional verification, then verification can be performed, but execution time becomes excessively long for large complex designs
Solution Approach 1:
The verification system is segmented into two independent but coordinated components: a software program executing on a computing unit and a testbench model executing on a reconfigurable hardware modeling device. This segmentation allows parallel execution of verification tasks that were previously sequential, significantly reducing total verification time while maintaining comprehensive coverage.
Solution Approach 2:
A communication interface acts as an intermediary between the computing unit and the reconfigurable hardware modeling device. This intermediary coordinates stimulus generation and response verification, enabling the two separate execution environments to work together seamlessly as a unified verification system.
2Reliability
If complete software stack is completed before hardware verification, then accurate software-hardware interaction can be verified, but overall verification process time is prolonged
Solution Approach 1:
The testbench model on the reconfigurable hardware modeling device performs preliminary hardware verification activities independently of the complete software stack. This preliminary action validates hardware functionality early in the development cycle, allowing software development to proceed in parallel without waiting for hardware completion.
Solution Approach 2:
The system maintains continuous verification activity through parallel execution: the software program continuously generates stimuli and validates responses while the testbench model simultaneously performs hardware validation. This continuous parallel action eliminates idle waiting periods and maximizes verification productivity throughout the entire process.
Data Source
AI summary
A verification system comprises: a reconfigurable hardware modeling device programmed to implement a hardware model of a circuit design; a first computing unit configured to execute a first software program; and a second computing unit configured to execute a testbench model of a second software program. The execution of the first software program and the testbench model of the second software program generates first stimuli and second stimuli for an operation of the hardware model of the circuit design, respectively. The first stimuli and the second stimuli are transmitted to the hardware model of the circuit design through a communication interface.