Concurrent Static Timing Analysis for Integrated Circuits
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Solution Overview
Problem
Current static timing analysis tools require significant processing resources, time, and man-hours due to the need for separate timing runs for each variable in integrated circuit design, making it inefficient and costly.
Innovation Solution
A method to concurrently generate multiple signals with different delays within a single timing run, using user-defined delay segments and timing points to model multiple logical paths, reducing the need for multiple analyses and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate timing runs are performed for each variable in static timing analysis, then measurement precision and reliability are improved, but processing time and resource consumption increase significantly
Solution Approach 1:
The patent merges multiple separate timing analysis runs into a single integrated timing run by concurrently modeling multiple delays between timing points. Instead of executing separate analyses for each delay variable, the system combines them into one unified analysis that processes all delay variations simultaneously, thereby maintaining measurement precision while dramatically reducing processing time and resource consumption.
Solution Approach 2:
The timing analysis system is enhanced to perform multiple timing analysis functions within a single run. By creating a universal timing analysis framework that can handle various delay scenarios (different delay values, different timing points, different logical paths) concurrently, the system achieves multi-functionality without requiring separate dedicated runs for each scenario.
2Reliability
If multiple separate timing runs are executed to account for different delay variables, then analysis completeness and reliability are improved, but processing resources and man-hours increase
Solution Approach 1:
Multiple timing analysis runs are merged into a single concurrent analysis that evaluates all delay variables simultaneously. The system combines the processing of different delay scenarios into one unified timing run, maintaining comprehensive coverage and reliability while improving productivity by eliminating redundant processing steps and reducing man-hour requirements.
Solution Approach 2:
The timing analysis system maintains continuous useful action by processing multiple delay variables concurrently within a single uninterrupted timing run. Instead of sequentially executing separate runs with idle time between them, the system continuously processes all timing scenarios in parallel, maximizing resource utilization and improving overall analysis efficiency.
3Measurement precision
If conventional static timing analysis is performed with multiple separate runs, then comprehensive timing verification is achieved, but computational complexity and resource usage increase
Solution Approach 1:
The patent simplifies the analysis system by merging multiple separate timing verification processes into a single integrated timing run. This consolidation reduces computational complexity and resource usage while maintaining comprehensive timing verification through concurrent modeling of multiple delays, effectively lowering the complexity burden without sacrificing verification completeness.
4Reliability
If separate timing analyses are conducted for different delay scenarios, then design robustness is improved, but time and resource consumption increase
Solution Approach 1:
The system merges multiple timing analyses for different delay scenarios into a single concurrent timing run, enabling comprehensive design robustness verification without proportionally increasing time and resource consumption. By processing all delay scenarios simultaneously rather than sequentially, the system maintains high design robustness while accelerating the design cycle.
Data Source
AI summary
An apparatus, program product and method perform static timing analysis on an integrated circuit design by concurrently modeling a plurality of timing delays associated with a connection between points in the design. The delays are conveyed in multiple clock signals of a single timing run of a static timing analysis operation. Multiple paths comprising logical user defined delay segments are assigned different delays. Only one signal may be permitted to propagate along each path.