Concurrent Status Register Reading via Bus Segmentation
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Solution Overview
Problem
Sequentially reading status information from multiple DRAM devices consumes valuable memory bandwidth, which could be used for other memory accesses, leading to performance degradation and increased power consumption.
Innovation Solution
Configuring each DRAM device to drive status information on a subset of the N-bit data bus and tri-state the remaining bits, allowing simultaneous reading of status information from multiple devices, thereby reducing the bus bandwidth dedicated to status read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If status information is read sequentially from multiple DRAM devices, then the reading operation is simple to implement, but the memory bandwidth is consumed and performance is degraded
Solution Approach 1:
The data bus is segmented into multiple subsets, with each DRAM device assigned to drive status information on a different subset. This allows parallel status reading from multiple devices simultaneously without consuming the entire memory bandwidth, resolving the contradiction between operational simplicity and bandwidth availability.
Solution Approach 2:
The patent transitions from sequential time-based status reading to parallel space-based reading by utilizing multiple bus subsets. This dimensional change from single-channel sequential access to multi-channel parallel access enables simultaneous status reads while preserving bandwidth for other memory operations.
2Loss of information
If status information is read from multiple DRAM devices using the full N-bit data bus, then complete status information is obtained, but the bus bandwidth is heavily consumed
Solution Approach 1:
The N-bit data bus is divided into multiple subsets, with each subset assigned to a specific DRAM device for status information transmission. This segmentation allows complete status information to be collected from multiple devices simultaneously while using only a portion of the total bus bandwidth at any given time, reducing power consumption.
Solution Approach 2:
The patent changes the parameter of bus utilization by having each device drive only a subset of the N bits rather than the full bus. This parameter change reduces the instantaneous bandwidth consumption and power usage while maintaining complete status information collection through parallel operations.
3Speed
If all N bits of the data bus are used for status information reading, then maximum data transfer rate is achieved, but bandwidth for other memory operations is reduced
Solution Approach 1:
The data bus is segmented into multiple subsets that can operate in parallel. Each subset maintains high transfer rates for status information from its assigned device, while other subsets remain available for memory operations, thereby preserving overall system throughput.
Solution Approach 2:
The patent merges status information transfer and memory operations by allowing them to occur simultaneously on different subsets of the data bus. This combination enables both functions to execute in parallel without interfering with each other, maintaining high speeds for both operations.
Data Source
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AI summary
Status information comprising data not stored in a memory array is efficiently read from a plurality of parallel memory devices sharing an N-bit data bus by configuring each memory device to drive the status information on a different subset M of the N bits, and tri-state the remaining N-M bits. Each memory device is additionally configured to drive zero, one or more data strobes associated with the subset M, and tri-state the remaining data strobes. A memory controller may simultaneously read status information from two or more memory devices in parallel, with each memory device driving a separate subset M of the N-bit bus. Each memory device may serialize the status information, and drive it on the subset M of the bus in burst form. Each memory device may include a configuration register initialized by a memory controller to define its subset M.