Concurrent Write Control Circuitry for Magnetoresistive Memory Tiles
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Solution Overview
Problem
Magnetoresistive memory circuits face slower write operations compared to read operations, limiting their performance and scalability as an alternative to current memory technologies.
Innovation Solution
The integration of resistive non-volatile memory bit cells arranged in memory tiles with concurrent write control circuitry allows for simultaneous write operations across multiple tiles, compressing overall write times and enhancing read/write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If magnetoresistive memory circuits are used to achieve non-volatile storage with high density and low power consumption, then memory density and power efficiency are improved, but write operation speed deteriorates and becomes substantially slower than read operation speed
Solution Approach 1:
The memory system is divided into multiple independent memory tiles, each capable of performing write operations simultaneously. The write control circuitry is segmented to independently manage write operations in different tiles, allowing parallel execution of write commands across multiple memory blocks without interfering with each other.
Solution Approach 2:
The patent transitions from sequential write operations in a single memory block to concurrent write operations across multiple spatial dimensions (multiple tiles). By adding the dimension of parallelism through multiple independent write paths, the system achieves improved overall write throughput while maintaining the inherent write speed characteristics of magnetoresistive memory cells.
2Device complexity
If conventional single-tile write control is used in magnetoresistive memory, then circuit complexity is kept simple, but overall write performance is limited and cannot achieve concurrency
Solution Approach 1:
The write control functionality is segmented into multiple independent control circuits, each dedicated to a specific memory tile. This segmentation allows each control circuit to independently manage write operations in its associated tile without waiting for other tiles to complete, thereby enabling concurrent write operations and improving overall productivity.
Solution Approach 2:
The write control circuitry is prepared in advance to simultaneously initiate write operations across multiple tiles upon receiving write commands. The control logic is designed to pre-coordinate the simultaneous activation of multiple write paths, allowing the system to maximize write throughput from the outset rather than sequentially processing writes.
3Use of energy by stationary object
If magnetoresistive memory is used as an alternative to flash memory and other non-volatile memories, then low power consumption and scalability are achieved, but write speed remains substantially slower than read speed
Solution Approach 1:
The memory system is divided into multiple independent memory tiles, each capable of performing write operations simultaneously. The write control circuitry is segmented to independently manage write operations in different tiles, allowing parallel execution of write commands across multiple memory blocks without interfering with each other.
Solution Approach 2:
The patent enables continuous write operations across multiple tiles by eliminating idle waiting time. While one tile is completing a write operation, other tiles can simultaneously perform write operations, ensuring that the write control resources remain continuously productive and maximizing the utilization of the magnetoresistive memory's write capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables write performance comparable to static random access memory (SRAM) or dynamic random access memory (DRAM) while maintaining a small physical footprint, addressing the speed disparity between write and read operations in magnetoresistive memory circuits.
Implementation Method 1
Memories employing magnetoresistive elements such as magnetic tunnel junction (MTJ) structures
Implementation Method 2
sensing differences in resistance between the two states in the magnetoresistive elements
Data Source
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AI summary
A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.