Conditional Branch to Indirect Memory Location
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computing environments, conditional branch instructions often require a spare general register to load branch locations, which is not always available, posing a challenge in program design, especially when the branch location needs to be dynamically determined at runtime.
Innovation Solution
A computer program product that facilitates processing by using a method to perform a conditional branch to an indirectly specified location in memory, where the branch address is obtained from a designated location in memory, determined by a condition code, and specified using a combination of fields including a base, index, and displacement fields, eliminating the need for additional registers beyond what is available.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a general register is used to form the branch location in conditional branch instructions, then the branch address can be readily accessed, but a spare general register must be available which is not always the case, limiting program design flexibility
Solution Approach 1:
The patent introduces an intermediary mechanism where the branch address is stored in memory rather than directly in a register. The instruction uses base register, index register, and displacement fields as intermediaries to compute the effective address of the branch target in memory, eliminating the need for a spare general register while maintaining branch address accessibility.
Solution Approach 2:
The patent moves the branch address from the register dimension to the memory dimension. Instead of storing the branch address directly in a general register, the address is stored in memory and accessed through a combination of base register, index register, and displacement fields, effectively adding a memory access dimension to the branch instruction.
2Reliability
If the branch location is specified directly in the instruction, then the branch address is known at compile time, but this limits dynamic branching capability at runtime
Solution Approach 1:
The patent makes the branch address dynamic by storing it in memory rather than hardcoding it in the instruction. The effective address is computed at runtime using base register, index register, and displacement fields, allowing the branch target to be determined dynamically during program execution rather than being fixed at compile time.
Solution Approach 2:
The patent performs preliminary actions by preparing the branch address components (base register value, index register value, and displacement) before the actual branch execution. These components are combined at runtime to form the final branch address, enabling dynamic branching while maintaining structured address computation.
3Ease of operation
If additional registers are provided for branch address loading, then branch operations become simpler, but the register file size and processor complexity increase
Solution Approach 1:
The patent makes existing registers multi-functional. The base register and index register, which can be used for various purposes, are also used for branch address computation. This eliminates the need for dedicated spare registers for branching, reducing register file size while maintaining branch operation simplicity through the use of existing register resources.
Solution Approach 2:
The patent changes the parameters of the branch instruction by introducing displacement fields and modifying how the effective address is computed. Instead of requiring a dedicated register, the instruction uses a combination of base register, index register, and displacement parameters to compute the branch address, reducing the need for additional registers while maintaining operational simplicity.
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
An instruction to perform a conditional branch to an indirectly specified location is executed. A branch address is obtained from a location in memory, the location in memory designated by the instruction. A determination is made,based on a condition code of another instruction, whether a branch is to occur, and a branch to the branch address is performed, based on determining the branch is to occur.