Conditional Cache Line Ownership for Multi-Core Systems

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Solution Overview

Problem

In shared memory multi-core processor systems, unnecessary updates to memory locations due to high spatial locality and thread data sharing lead to performance degradation, as they result in redundant cache line invalidations and increased message traffic, even when the value to be written is the same as the existing value.

Innovation Solution

Implementing new hardware support and instructions for conditional store operations, such as CondScalarStore and CondVectorStore, which only issue a request for cache line ownership if the new value differs from the existing value, thereby reducing unnecessary read and request for ownership messages and data movement between core caches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a core broadcasts Read for Ownership or Request for Ownership message to establish cache line ownership, then cache line coherency is maintained, but unnecessary message traffic and cache invalidations occur when the value to be written is the same as the existing value

Engineering Contradiction:
Improvecache line coherencyVSAvoidmessage traffic
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent performs a preliminary read of the cache line value before issuing ownership requests. By checking the current value against the intended write value in advance, the system determines whether an ownership request is necessary, thereby preventing unnecessary message traffic and cache invalidations when values match.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by reading the current cache line value and comparing it with the intended write value. This feedback mechanism enables the core to make an informed decision about whether to proceed with ownership requests, avoiding redundant operations when no actual update is needed.

Inventive Principle:
Principle #23Feedback

2Productivity

If conditional checks are added to prevent unnecessary updates, then performance degradation is reduced, but code size increases and compiler optimizations are limited

Engineering Contradiction:
ImproveperformanceVSAvoidcode size
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces software-based conditional checks with hardware-level mechanisms. The caching agent automatically performs value comparison and conditionally issues ownership requests, eliminating the need for explicit conditional code and associated branches while preserving performance benefits.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The caching agent autonomously determines whether ownership requests are necessary by comparing cache line values, without requiring explicit software intervention. This self-service approach eliminates manual conditional checks while maintaining performance optimizations.

Inventive Principle:
Principle #25Self-service

3Reliability

If Read for Ownership messages are issued frequently, then cache line coherency is ensured, but cache miss rate increases and performance decreases

Engineering Contradiction:
Improvecache line coherencyVSAvoidcache miss rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary value comparison before issuing ownership requests to prevent unnecessary cache invalidations. By checking whether the intended write value differs from the current cache line value in advance, the system avoids triggering cache misses when no actual update is required.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from reading cache line values to intelligently determine whether ownership requests should be issued. This feedback-driven approach reduces unnecessary cache invalidations and associated cache misses while maintaining coherency when updates are actually needed.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11550721B2Method and apparatus for smart store operations with conditional ownership requests
Publication Date: 2023.01.10 INTEL CORP
  • US11550721B2 patent drawing
  • US11550721B2 patent drawing
  • US11550721B2 patent drawing

AI summary

Method and apparatus implementing smart store operations with conditional ownership requests. One aspect includes a method implemented in a multi-core processor, the method comprises: receiving a conditional read for ownership (CondRFO) from a requester in response to an execution of an instruction to modify a target cache line (CL) with a new value, the CondRFO identifying the target CL and the new value; determining from a local cache a local CL corresponding to the target CL; determining a local value from the local CL; comparing the local value with the new value; setting a coherency state of the local CL to (S)hared when the local value is same as the new value; setting the coherency state of the local CL to (I)nvalid when the local value is different than the new value; and sending a response and a copy of the local CL to the requester. Other embodiments include an apparatus configured to perform the actions of the methods.