Conditional Instruction Distribution Across Pipelines with Different Latencies
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Solution Overview
Problem
Current processor technologies face challenges in accurately predicting the outcomes of conditional instructions, leading to inefficiencies and increased workload due to mispredictions, especially with the increasing complexity and width of execution pipelines.
Innovation Solution
Incorporating a bias prediction circuit and an instruction prediction circuit within the processor to provide separate predictions for conditional instructions, allowing predictively-biased instructions to bypass the instruction prediction circuit and reduce overall workload by improving prediction accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single instruction prediction circuit is used to predict all conditional instructions, then the device complexity is reduced, but the prediction accuracy decreases for diverse conditional patterns
Solution Approach 1:
The prediction circuit is segmented into multiple specialized sub-circuits: a bias prediction circuit for detecting biased conditional instructions and an instruction prediction circuit for handling non-biased instructions. This segmentation allows each sub-circuit to be optimized for its specific function, improving overall prediction accuracy while managing complexity through functional specialization.
Solution Approach 2:
Different prediction strategies are applied to different types of conditional instructions based on their local characteristics. Biased conditional instructions use bias prediction with higher accuracy, while non-biased instructions use instruction prediction. This local quality approach ensures that each instruction type receives the most appropriate prediction method.
2Productivity
If all conditional instructions go through the instruction prediction circuit, then the device complexity is reduced, but the processing time increases due to unnecessary prediction operations
Solution Approach 1:
The bias prediction circuit performs preliminary prediction on conditional instructions before they reach the instruction prediction circuit. This preliminary action filters out biased instructions that can be resolved quickly, preventing them from undergoing the more complex instruction prediction process and thus reducing overall processing time.
Solution Approach 2:
Biased conditional instructions are extracted from the main instruction flow after bias prediction and handled separately through a different execution path. This extraction removes unnecessary instructions from the complex prediction pipeline, improving processing speed for the remaining instructions.
3Productivity
If multiple execution pipelines with different latencies are used, then the processing efficiency for mispredictions is improved, but the device complexity increases
Solution Approach 1:
The execution system is segmented into multiple pipelines with different latency characteristics: a first execution pipeline for normal instruction execution and a second execution pipeline specifically for handling mispredicted instructions. This segmentation allows optimized handling of different instruction types, improving misprediction recovery efficiency.
Solution Approach 2:
A misprediction detection mechanism acts as an intermediary between the execution pipelines and the prediction circuits. It monitors execution outcomes and triggers appropriate pipeline switching or flushing actions, enabling efficient misprediction handling without requiring complex direct communication between all system components.
4Productivity
If speculative execution is enabled to improve throughput, then the productivity increases, but the loss of time increases when mispredictions occur due to discarded speculative work
Solution Approach 1:
The system dynamically changes execution parameters based on prediction confidence. Instructions predicted by the bias prediction circuit (which has higher accuracy for biased conditions) are executed with different pipeline parameters compared to those handled by the instruction prediction circuit. This parameter adaptation reduces the frequency and impact of mispredictions, lowering the time penalty.
Data Source
AI summary
A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.