Conditional Instruction Prediction for Parallel Execution

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Solution Overview

Problem

Conditional instructions in microprocessor architectures often require serialization due to data dependencies, leading to reduced parallelism and execution speed, resulting in wasted pipeline resources.

Innovation Solution

A device and method that predict the execution results of predicate and conditional instructions, allowing for parallel execution based on extracted information, using a conditional instruction prediction module to manage parallel execution resources and handle prediction accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conditional instructions are serialized to ensure data dependency correctness, then execution accuracy is maintained, but execution speed and parallelism are significantly reduced

Engineering Contradiction:
Improveexecution accuracyVSAvoidexecution speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by predicting the execution results of predicate instructions before they are actually executed. The prediction unit generates predicted values in advance, allowing conditional instructions to be executed in parallel based on these predictions rather than waiting for actual predicate results, thus maintaining execution accuracy while improving speed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a prediction unit as an intermediary between predicate instructions and conditional instructions. This prediction unit generates predicted execution results that mediate the data dependency, enabling parallel execution while maintaining correctness through subsequent validation against actual results

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conditional instructions are serialized to maintain data dependency, then correct execution is ensured, but pipeline resources are wasted

Engineering Contradiction:
Improveexecution correctnessVSAvoidpipeline resource waste
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

By performing prediction in advance, the system prevents pipeline stalls before they occur. The prediction unit operates ahead of time, allowing the pipeline to remain full and productive rather than stalling to wait for predicate results, thus reducing energy waste while maintaining correctness

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by validating predicted results against actual execution outcomes. When predictions are correct, parallel execution proceeds; when incorrect, the system detects the error and corrects it, ensuring execution correctness while minimizing pipeline resource waste through efficient error handling

Inventive Principle:
Principle #23Feedback

3Productivity

If parallel execution resources are provided to optimize throughput, then execution efficiency is improved, but data dependencies cause serialization bottlenecks

Engineering Contradiction:
Improveexecution throughputVSAvoidexecution control complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the execution process into prediction, execution, and validation phases. The prediction unit handles dependency resolution separately from the main execution pipeline, allowing parallel execution resources to operate independently without being blocked by data dependencies, thus improving throughput while managing complexity through clear separation of concerns

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10379858B2Method and apparatus for executing conditional instruction predicated on execution result of predicate instruction
Publication Date: 2019.08.13 SPREADTRUM HONG KONG LTD
  • US10379858B2 patent drawing
  • US10379858B2 patent drawing
  • US10379858B2 patent drawing

AI summary

A device for executing conditional instructions is provided. The device includes one or more processors and a memory unit including a plurality of registers storing at least a predicate instruction and a conditional instruction, executable by the one or more processors. Execution of the conditional instructions is predicated on execution results of the predicate instruction. The one or more processors are configured to extract predicate-determining information of the predicate instruction and conditional instruction information of the conditional instruction; predict execution results for the predicate instruction and the conditional instruction based on the predicate-determining information and the conditional instruction information; and execute the predicate instruction and the conditional instruction in parallel, based on the predicted execution results for the predicate instruction and the conditional instruction.