Conditional Latch Reset Logic for Lower Power and Noise
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Solution Overview
Problem
Existing latch reset circuitry in sequential circuit devices leads to undesired power dissipation due to parasitic capacitances and cross-coupling noise, necessitating an improved method for conditional reset that reduces power consumption and noise.
Innovation Solution
A latch circuit device and method utilizing a logic circuit comprising a NAND gate, inverters, and an OR gate, with a transistor coupled to the OR gate, which conditionally resets latches based on their output state values, reducing unnecessary resets and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset control signal is asserted to reset storage elements, then the storage elements are reset to a known state, but power dissipation increases due to parasitic capacitances
Solution Approach 1:
The patent applies local quality by making the reset operation selective rather than universal. The logic circuit evaluates the current state of each latch and applies the reset signal only to specific latches that need resetting, rather than resetting all latches in the circuit. This localized approach reduces the overall power dissipation while maintaining the reliability of necessary reset operations.
Solution Approach 2:
The patent implements partial action by conditionally applying the reset signal to only some latches based on their current state. The logic circuit determines which latches require resetting and applies the reset control signal selectively, avoiding the excessive action of resetting all latches regardless of their state. This reduces unnecessary power consumption while ensuring reliable reset where needed.
2Reliability
If reset operations are performed on multiple latches, then all latches are reset to a known state, but power surge current events increase
Solution Approach 1:
The logic circuit applies local quality by selectively resetting only the specific latches that require it, based on their current state evaluation. This localized reset approach prevents simultaneous resetting of all latches, thereby reducing the cumulative power surge current events while maintaining latch state consistency where necessary.
Solution Approach 2:
The patent uses partial action by performing reset operations on only the necessary subset of latches rather than all latches. The logic circuit identifies which latches need resetting and applies the reset signal conditionally, avoiding the excessive action of universal resetting. This reduces power surge current events while ensuring reliability of the reset function.
3Reliability
If all latches are reset simultaneously, then all storage elements are in a known state, but cross-coupling noise increases
Solution Approach 1:
The patent applies local quality by implementing selective resetting of individual latches based on their specific needs. The logic circuit evaluates each latch's state and applies the reset signal locally to only those latches that require it, rather than simultaneously resetting all latches. This reduces cross-coupling noise while maintaining latch state predictability where needed.
Solution Approach 2:
The patent implements partial action by resetting only the necessary latches rather than all latches simultaneously. The logic circuit determines which latches require resetting and applies the reset signal conditionally to that subset, avoiding the excessive action of universal simultaneous resetting. This reduces cross-coupling noise while ensuring predictability of latch states that require resetting.
Data Source
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AI summary
A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal