Conditional Latch Reset Circuit for Lower Power and Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing latch reset circuitry in sequential circuit devices leads to undesired power dissipation due to parasitic capacitances, resulting in increased power consumption and noise, particularly when all latches are reset simultaneously.
Innovation Solution
A conditional reset logic circuit that selectively resets latches based on their output state values, reducing the number of reset operations and minimizing simultaneous resets across adjacent latches, thereby reducing power consumption and cross-coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all latches are reset simultaneously using traditional reset circuitry, then the latches are ensured to be in a known state, but power dissipation increases due to parasitic capacitances
Solution Approach 1:
The patent applies local quality by making the reset operation selective rather than uniform across all latches. The reset logic circuit examines the state of each latch and applies reset only to those latches that are not already in the desired state, thereby localizing the reset action to specific latches that need it. This reduces unnecessary switching activity and associated power dissipation from parasitic capacitances while still ensuring all latches end up in a known state.
2Reliability
If reset operations are performed on all latches, then complete reset functionality is achieved, but power surge current events increase
Solution Approach 1:
The patent implements partial action by performing reset operations on only the subset of latches that require resetting, rather than forcing a reset on all latches. The reset logic circuit determines which latches need resetting by examining their current state and applying the reset signal conditionally. This partial reset approach achieves complete reset functionality for the necessary latches while avoiding unnecessary reset operations that would generate surge current events.
3Productivity
If simultaneous reset operations are performed on adjacent latches, then reset efficiency is maintained, but cross-coupling noise increases
Solution Approach 1:
The patent applies dynamics by making the reset operation adaptive rather than static. The reset logic circuit dynamically evaluates the state of each latch and determines the reset sequence based on actual conditions. This can result in staggered or non-simultaneous reset operations for adjacent latches when their states differ, thereby reducing cross-coupling noise while maintaining overall reset efficiency. The system adapts the reset timing and sequence to the actual state of the latches rather than following a fixed simultaneous reset pattern.
Data Source
AI summary
A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.