Conditional Latch Signal Generation for Low-Power Race-Free Latches
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Solution Overview
Problem
Integrated circuit latches face issues with race conditions and unnecessary power dissipation due to the implementation of flip flop devices, which require continuous latching signals regardless of data state changes.
Innovation Solution
A latching signal generator that compares latch input data with stored latch data to determine when a state change is necessary, generating a latching signal only during active cycles of the clock signal and suppressing it when data is unchanged, thereby reducing power consumption and alleviating race conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If flip flop devices are used to implement latches, then data storage function is achieved, but unnecessary power dissipation occurs due to continuous latching signals
Solution Approach 1:
The latching signal is generated only when necessary (when input data differs from stored data) rather than continuously, applying partial action to eliminate unnecessary power dissipation while maintaining reliable data storage functionality
Solution Approach 2:
The determination circuit compares current input data with previously stored latch data and uses this feedback to control latching signal generation, enabling the system to adapt its behavior based on actual data state changes and avoid race conditions
2Reliability
If continuous latching signals are provided to flip flop devices, then race conditions are prevented, but power consumption increases unnecessarily
Solution Approach 1:
The latching signal is provided only during the portions of clock cycles when actual data state changes are required, rather than continuously, thereby maintaining race condition prevention while eliminating wasteful power consumption during unchanged states
Solution Approach 2:
The latching signal is generated periodically only when data changes occur, synchronized with clock cycles but conditional on actual data state transitions, rather than maintaining continuous periodic signaling that wastes energy
3Productivity
If latching signals are generated during every clock cycle, then data updates are ensured, but power dissipation increases due to unnecessary signal generation
Solution Approach 1:
The latching signal generation is applied partially - only during clock cycles when input data differs from stored data - maintaining necessary data update frequency while eliminating energy waste from generating signals during unchanged states
Solution Approach 2:
The determination circuit automatically detects when data updates are necessary by comparing input data with stored data, and self-regulates latching signal generation accordingly, eliminating the need for external control while optimizing power consumption
Data Source
AI summary
Some of the embodiments of the present disclosure provide a latching signal generator, comprising a plurality of inputs configured to receive a clock signal, latch input data, and latch data, wherein the latch input data and the latch data are associated with a latch and wherein the latching signal generator is configured; to provide a latching signal to a latch; and a determination circuit that is configured to cause the latching signal generator to provide the latching signal based on during an active cycle of the clock signal, in response to a determination that the input latch data is different than the latch data. Other embodiments are also described and claimed.