Conditional Load Store for DSP Tail Loop Optimization

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Solution Overview

Problem

Current digital signal processing (DSP) methods are inefficient in handling leftover bytes less than a vector length, leading to increased code size and performance impacts due to the need for multiple loops to manage 8-byte, 4-byte, and 1-byte lengths, which complicates the processing of unaligned data.

Innovation Solution

The introduction of unaligned masked load and store instructions, such as DVPMASKLDDQU and DVPMASKSTDQU, which allow for conditional loading and storing of data elements based on mask bits, enabling efficient processing of leftover bytes without faults, thereby reducing the complexity and size of tail loops.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple loops are used to manage leftover bytes of different lengths (8-byte, 4-byte, 2-byte, 1-byte), then processing completeness is improved, but code size and device complexity increase

Engineering Contradiction:
Improveprocessing completenessVSAvoidcode size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple separate loops (tailloop0 for 8-byte, tailloop1 for 4-byte, tailloop2 for 2-byte, tailloop3 for 1-byte) into a single unified loop structure. This unified loop uses a mask register to selectively process different byte lengths in one iteration, eliminating the need for four separate loop implementations and reducing code size while maintaining processing completeness.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified loop structure serves multiple functions simultaneously: it can process 8-byte, 4-byte, 2-byte, and 1-byte leftovers within the same loop body by using mask bits to control which data elements are processed. This multi-functional approach replaces four specialized loops with one universal loop that adapts to different processing needs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple loops are used to manage leftover bytes of different lengths, then processing completeness is improved, but processing time and energy consumption increase

Engineering Contradiction:
Improveprocessing completenessVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By combining four separate loop iterations into one unified loop that processes all leftover byte lengths simultaneously using mask control, the patent reduces the total number of loop iterations and associated overhead, thereby improving processing efficiency while maintaining complete processing of all leftover bytes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified loop structure enables continuous processing of different leftover byte lengths without the interruptions and restarts that would occur with multiple separate loops. The mask register allows the loop to continuously select and process the appropriate data elements in each iteration, eliminating idle time and improving overall processing throughput.

Inventive Principle:
Principle #20Continuity of useful action

3Adaptability or versatility

If unaligned data is processed with traditional methods, then compatibility is maintained, but processing efficiency decreases due to fault risks

Engineering Contradiction:
ImprovecompatibilityVSAvoidprocessing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The mask register acts as an intermediary between the unaligned data and the processing logic. By using mask bits to selectively enable or disable processing of specific data elements, the system can safely handle unaligned data without causing faults, while maintaining compatibility with existing data formats and processing requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240004660A1Conditional load and/or store
Publication Date: 2024.01.04 INTEL CORP
  • US20240004660A1 patent drawing
  • US20240004660A1 patent drawing
  • US20240004660A1 patent drawing

AI summary

Techniques for conditional loads and/or stores using an instance of a single instruction are described. In some examples, the instance of the single instruction at least includes one or more fields for an opcode, one or more fields to reference a first source operand, one or more fields to reference a second source operand, and one or more fields to reference a destination memory location, wherein the opcode indicates execution circuitry is to conditionally store data elements from data element positions of the second source operand into corresponding data element positions of the memory location of the referenced destination operand based on masking information stored in the referenced first source operand. In some examples, the masking information is provided by a value of a most significant bit position of each data element of the first source operand.