Conditional Microprocessor Activation for VoIP Power Reduction
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Solution Overview
Problem
Current data communication devices require dual-core processors for effective real-time processing, which is complex, expensive, and power-intensive, especially with the need for digital signal processors (DSPs) that increase costs and power consumption.
Innovation Solution
Implementing a hardware-centric approach with a single microprocessor that conditionally activates and deactivates for packet processing, using a Reduced Instruction Set Computer (RISC) microprocessor to perform VoIP and VoWLAN functions without a dedicated DSP, optimizing data locality and processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-core processor architecture is employed to handle real-time processing requirements, then processing capability and reliability are improved, but device complexity, manufacturing cost, and power consumption increase
Solution Approach 1:
The patent implements dynamic processor activation where the second processor is conditionally activated only when real-time processing is required, and deactivated during non-real-time periods. This dynamic operation mode allows the system to maintain dual-processor reliability when needed while reducing complexity and power consumption during normal operation.
Solution Approach 2:
The system employs periodic activation of the second processor based on real-time processing requirements. The processor alternates between active and inactive states, with activation occurring periodically when real-time constraints demand processing capability, thus balancing reliability needs with power consumption and complexity reduction.
2Reliability
If dual-core processor architecture with DSP is employed to handle real-time processing requirements, then processing capability is improved, but manufacturing cost increases
Solution Approach 1:
The system dynamically activates the DSP only when real-time processing is required, allowing manufacturers to include DSP capability without permanently incurring its high operational cost. This dynamic approach makes the expensive component economically viable by limiting its use to essential real-time scenarios.
Solution Approach 2:
The first processor is designed to handle both general-purpose applications and real-time processing tasks when the second processor is inactive. This multi-functionality reduces the need for dedicated expensive DSP hardware in all operating scenarios, thereby lowering manufacturing costs while maintaining real-time capability when needed.
3Reliability
If dual-core processor architecture is employed to handle real-time processing requirements, then processing capability is improved, but power consumption increases
Solution Approach 1:
The system implements dynamic power management where the second processor transitions between active and sleep states based on real-time processing demands. This dynamic state change significantly reduces average power consumption while ensuring real-time processing capability is available when required.
Solution Approach 2:
The second processor operates in periodic bursts, activating only when real-time processing is needed and remaining inactive during non-real-time periods. This periodic operation pattern dramatically reduces overall power consumption compared to continuous operation, extending battery life while maintaining reliability.
4Device complexity
If single processor is employed to reduce complexity and cost, then device complexity and manufacturing cost are reduced, but real-time processing capability deteriorates due to interrupt conflicts
Solution Approach 1:
The system dynamically switches between single-processor and dual-processor modes based on task requirements. During non-real-time periods, only the first processor operates, simplifying control. When real-time processing is needed, the second processor is activated to handle time-critical interrupts, thus maintaining real-time capability without permanent dual-processor complexity.
Solution Approach 2:
The processing tasks are segmented into real-time and non-real-time categories. The first processor handles non-real-time applications, while the second processor is dedicated to real-time processing when activated. This segmentation allows each processor to specialize in its designated task type, maintaining real-time capability while reducing overall system complexity through conditional activation.
5Use of energy by moving object
If single processor is employed to reduce power consumption, then power consumption is reduced, but real-time processing capability deteriorates due to interrupt conflicts
Solution Approach 1:
The system dynamically activates the second processor only during real-time processing requirements, allowing the first processor to handle low-power non-real-time tasks alone during other periods. This dynamic activation strategy minimizes average power consumption while ensuring real-time processing capability is available when needed.
Solution Approach 2:
The second processor operates periodically only when real-time processing is required, remaining inactive during non-real-time periods to conserve power. This periodic activation pattern reduces overall power consumption compared to continuous dual-processor operation while maintaining real-time processing reliability when demanded.
Data Source
AI summary
Conditional activation and deactivation of a microprocessor. A hardware portion of an apparatus performs packet processing on received data, where the hardware portion selectively decodes the received data. A microprocessor performs data processing on decoded data, where the microprocessor is conditionally activated for performing the data processing and is conditionally deactivated when not performing the data processing. An output portion receives processed data and audibly renders the processed data without requiring the microprocessor.