Conditional Modular Subtraction Instruction for Faster HE Arithmetic

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Solution Overview

Problem

Homomorphic encryption (HE) operations, particularly polynomial multiplication in finite fields, are computationally expensive and pose a bottleneck in privacy-preserving machine learning (PPML) due to inefficient polynomial multiplication and modular operations like NTT, which are not adequately optimized.

Innovation Solution

Introduce a set of instructions, including the vpcondsubuq instruction, to optimize forward and inverse NTT operations and element-wise modular multiplication by performing conditional subtraction, reducing the number of instructions required for HE operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional instructions are used for HE operations, then computational correctness is maintained, but computational expense and execution time increase significantly

Engineering Contradiction:
Improveexecution speed of HE operationsVSAvoidnumber of instructions required
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines multiple sequential instructions into a single conditional modular subtraction instruction. Specifically, it merges comparison operations, conditional branching, and subtraction operations into one atomic instruction that performs modular subtraction only when needed, thereby reducing the total instruction count and improving execution speed while maintaining computational correctness

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a new instruction parameter type (the conditional modular subtraction instruction) that changes the operational parameters of the CPU instruction set. This new instruction type enables direct modular arithmetic operations without requiring multiple separate instructions, thereby optimizing the execution parameters for HE workloads

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If multiple sequential instructions are used for conditional subtraction, then operational flexibility is maintained, but execution time increases

Engineering Contradiction:
Improveexecution time of subtraction operationsVSAvoidinstruction complexity
Core Design Contradiction:
Loss of timeVSEase of operation

Solution Approach 1:

The patent merges comparison, branching, and subtraction operations into a single atomic conditional modular subtraction instruction. This eliminates the need for multiple sequential instructions while maintaining operational flexibility, thereby reducing execution time without sacrificing ease of operation

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conditional modular subtraction instruction is designed to automatically determine whether subtraction is needed based on the operands' values. The instruction internally performs the comparison and conditional logic, making the system self-determining about when modular subtraction is required, thereby reducing execution time without requiring external control complexity

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20260111232A1Conditional modular subtraction instruction
Publication Date: 2026.04.23 INTEL CORP
  • US20260111232A1 patent drawing
  • US20260111232A1 patent drawing
  • US20260111232A1 patent drawing

AI summary

One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand and a second source operand and second circuitry including a processing resource to execute the decoded instruction, wherein responsive to the decoded instruction, the processing resource is to output a result of first source operand data minus second source operand data in response to a determination by the processing resource that the first source operand data is greater than or equal to the second source operand data, otherwise the processing resource is to output the first source operand data.