Conditional Multi-Store Synchronization Mechanism

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Solution Overview

Problem

Current synchronization techniques, such as load-linked/store-conditional (LL/SC) and transactional memory, face limitations in coordinating competing computations, including restrictions on the number of stores that can be executed and the need for complex implementation requirements, which hinder concurrency and scalability.

Innovation Solution

The introduction of conditional multi-store synchronization mechanisms allows a program to store values to memory locations only if a flagged memory location has not changed, enabling multiple conditional stores without the need for buffering, thus facilitating concurrency and scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transactional memory monitors multiple locations to prevent stores from taking effect, then synchronization reliability is improved, but the number of stores that can be executed is limited

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidnumber of stores that can be executed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the synchronization mechanism into two distinct parts: (1) a monitor set that tracks multiple monitored locations for reliability, and (2) a store buffer that independently manages individual store operations. This segmentation allows each store to be buffered and potentially committed independently, rather than requiring the entire transaction to complete atomically. The store buffer operates as a separate queue that can hold multiple store operations while the monitor set continues to track location changes, thus resolving the contradiction between monitoring multiple locations and executing arbitrary numbers of stores.

Inventive Principle:
Principle #1Segmentation

2Reliability

If transactional memory buffers all stores until transaction completion, then synchronization correctness is improved, but implementation complexity increases

Engineering Contradiction:
Improvesynchronization correctnessVSAvoidimplementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the transactional memory system into independent components: a monitor set for tracking location changes, a store buffer for holding store operations, and a commit mechanism for finalizing stores. The store buffer operates independently with its own head and tail pointers, allowing stores to be queued without blocking the monitoring of multiple locations. This modular segmentation reduces implementation complexity compared to a monolithic transactional memory system that must buffer all stores until complete transaction validation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The store buffer performs preliminary actions by accepting and queuing store operations before the transaction is fully validated. Instead of requiring all stores to be held until transaction completion, the buffer preliminarily stores operations in a structured format with head/tail pointers, enabling incremental commitment of stores as the transaction progresses. This preliminary buffering action simplifies the implementation by allowing stores to be prepared in advance without requiring complete transaction validation first.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If store buffer size is limited, then memory usage is reduced, but the number of conditional stores is constrained

Engineering Contradiction:
Improvememory usageVSAvoidnumber of conditional stores
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The store buffer implements dynamic management through head and tail pointers that adaptively track the current position in the buffer. The buffer size can effectively grow and shrink based on the number of pending stores and commit operations, rather than requiring a fixed large allocation. This dynamic structure allows the system to support an arbitrary number of conditional stores by efficiently utilizing available buffer space, resolving the contradiction between limited memory usage and the ability to handle many conditional stores.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7480771B2Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged
Publication Date: 2009.01.20 ORACLE AMERICAN INC
  • US7480771B2 patent drawing
  • US7480771B2 patent drawing
  • US7480771B2 patent drawing

AI summary

We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.