Conditional Rotation Circuit for Phase Estimation

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Solution Overview

Problem

Existing signal processing systems face inefficiencies in estimating the phase and magnitude of complex valued input data, with methods like CORDIC algorithms and lookup tables being either computationally costly or impractical for increasing data throughput.

Innovation Solution

A circuit design that includes a first processing stage to calculate the absolute values of input components and a second processing stage for conditional rotation, reducing the phase range from 0° to 45° to approximately -15°, enabling efficient phase and magnitude estimation using basic digital circuitry components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If CORDIC algorithm is used to estimate phase, then phase estimation accuracy is improved, but processing time increases due to multiple iterations

Engineering Contradiction:
Improvephase estimation accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The phase estimation problem is segmented into two independent stages: magnitude estimation using the conditional rotation circuit, and phase estimation using a separate LUT. This segmentation allows each stage to be optimized independently, with the magnitude stage using simple comparisons and additions rather than iterative calculations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit performs preliminary conditional rotation to transform the input coordinates into a standardized range before phase estimation. By pre-processing the coordinates through the conditional rotation logic (comparing x and y, swapping if necessary, rotating by 45° when needed), the system prepares the data in a form that enables direct LUT lookup, eliminating the need for iterative CORDIC operations.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If lookup table is used to read phase of input, then processing speed is improved, but memory size grows exponentially with input bits

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory size
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system changes the parameter range through conditional rotation, transforming arbitrary input coordinates into a standardized range where x ≥ y ≥ 0. This parameter transformation reduces the effective dimensionality of the LUT, as the rotation angle only needs to cover a limited angular range rather than the full 360°, significantly reducing memory requirements while maintaining processing speed.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If approximation formula is used for calculating phase, then computational complexity is reduced, but accuracy decreases and still requires multiple operations

Engineering Contradiction:
Improvecomputational complexityVSAvoidphase estimation accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The circuit extracts and handles the problematic case separately: when both x and y are positive and x < y, the system performs a conditional 45° rotation to swap the coordinates. This extraction of the problematic quadrant allows the main LUT to handle the majority of cases directly, while the rotated cases are handled through a simple coordinate transformation followed by LUT lookup, maintaining both simplicity and accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10177902B2Circuit and method for processing data
Publication Date: 2019.01.08 STICHTING IMEC NEDERLAND
  • US10177902B2 patent drawing
  • US10177902B2 patent drawing
  • US10177902B2 patent drawing

AI summary

Systems and methods for processing data including a first and second component are described. An example circuit includes a processing stage arranged to calculate absolute values of the first component and the second component, and to output, at a first output, a maximum value of the absolute value of the first component and the absolute value of the second component, and, at a second output, a minimum value of the absolute value of the first component and the absolute value of the second component. The circuit includes a processing stage arranged to output, in response to the maximum value being greater than the minimum value times four, a value corresponding to the maximum value, and to output, in response to the maximum value being smaller than the minimum value times four, a value corresponding to a sum of seven times the maximum value and four times the minimum value.