Selective Conditional Stall for Hardware Circuit Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current hardware-based circuit verification methods, such as software simulation and emulation, are inefficient for large complex designs like SoC, particularly due to long design paths that limit clock frequency and slow down verification processes.
Innovation Solution
The implementation of a reconfigurable hardware modeling device with path-breaking circuit devices that divide design paths into segments, generating stall signals to suppress unnecessary state updates, allowing the hardware model to operate at a higher clock frequency by selectively conditioning stalls and generating new clock signals based on signal changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware-based emulation is used for circuit verification, then verification speed is improved compared to software simulation, but long design paths limit the clock frequency and reduce verification productivity
Solution Approach 1:
The design path is divided into multiple segments by inserting path-breaking circuit devices at strategic locations. Each segment can be independently clocked, allowing the overall design path to be broken into shorter segments that can operate at higher clock frequencies without being constrained by the original long path delay
Solution Approach 2:
The system dynamically adjusts clocking behavior by generating stall signals when signal changes are detected at path-breaking locations. This dynamic stall mechanism allows the circuit to operate at higher clock frequencies by pausing state updates only when necessary to maintain verification accuracy, rather than being constrained by the maximum delay of the entire design path
2Productivity
If the clock frequency is increased to speed up verification, then productivity is improved, but long design paths cause timing violations and verification errors
Solution Approach 1:
The path-breaking circuit devices monitor signal changes and generate stall signals based on detected transitions. This feedback mechanism ensures that state elements only update when actual signal changes occur, maintaining timing accuracy even at higher clock frequencies by preventing premature or spurious state updates that would violate timing requirements
3Speed
If path-breaking circuit devices are inserted to divide design paths, then clock frequency can be increased, but device complexity increases
Solution Approach 1:
The path-breaking circuit devices serve multiple functions: they divide the design path into segments, detect signal changes, generate stall signals, and control state element updates. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity while achieving higher clock frequencies
Data Source
AI summary
Various aspects of the present disclosed technology relate to techniques for selective conditional stall for speeding up hardware-based circuit verification. A path-breaking circuit device is inserted into a location of a design path configured to generate a stall signal indicating whether a change of signal between a pair of neighboring clock cycles of a clock signal is detected at the location. The stall signal is used to directly or indirectly suppress, when the change of signal between the pair of neighboring clock cycles is detected, the next state updating for state element models in the hardware model of circuit design. The design path is usually the critical design path. The insertion location is usually selected to be a location where the signal does not change frequently.