Conditional Writeback Scheme for Memory Security

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Solution Overview

Problem

Existing memory devices face challenges in efficiently implementing security measures and conditional writeback schemes, which can lead to delays in data storage and processing bottlenecks due to limited processing resources.

Innovation Solution

The implementation of a conditional writeback scheme in memory devices, where data storage is conditional based on the results of a series of operations, allowing for the use of portions of the memory device as transactional memory, enabling atomic and irreducible store commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If security measures are implemented before data storage, then data security is improved, but data storage time is delayed

Engineering Contradiction:
Improvedata securityVSAvoiddata storage time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing security operations before data storage in advance. The system executes security checks and validations prior to writing data to memory, ensuring that security measures are established beforehand. This allows the memory device to maintain security protocols while managing the timing of data storage operations, resolving the contradiction between security implementation and storage speed.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple operations are performed before data storage, then data validation is improved, but processing bottleneck is worsened

Engineering Contradiction:
Improvedata validationVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary action by executing validation operations before data storage is attempted. Multiple validation checks are performed in advance to ensure data integrity and correctness. This preliminary validation approach allows the system to maintain high data validation standards while the memory device manages processing bottlenecks through conditional writeback mechanisms that can skip validation steps when appropriate.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies dynamics by making the validation process adaptive rather than static. The system dynamically adjusts the number and type of validation operations based on current processing conditions, data characteristics, and memory device state. This allows the system to maintain high validation standards while avoiding processing bottlenecks by reducing validation intensity when conditions permit.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If security operations are performed internally in memory device, then integration is improved, but processing resources are limited

Engineering Contradiction:
ImproveintegrationVSAvoidprocessing resources
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the memory device to perform multiple functions including data storage, security operations, and validation tasks. The memory device is configured to handle both its traditional storage function and security-related operations, reducing the need for separate dedicated security processing units. This multi-functional approach improves integration while managing processing resource requirements through efficient task scheduling and conditional execution.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12322468B2Conditional write back scheme for memory
Publication Date: 2025.06.03 MICRON TECHNOLOGY INC
  • US12322468B2 patent drawing
  • US12322468B2 patent drawing
  • US12322468B2 patent drawing

AI summary

Apparatuses and methods can be related to implementing a conditional write back scheme for memory. The data may be stored by memory cells of a memory array. The data may be moved to sense circuitry. The data can be conditionally held by the sense circuitry while a plurality of operations is performed. The results of the plurality of operations can dictate whether to commit the data to the memory cells.