Conditioning Logic Circuits for Faster CMOS Transitions
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Solution Overview
Problem
Existing digital logic circuits face challenges in achieving improved performance and reduced power dissipation while maintaining robustness, as complementary logic is robust but performance and power are negatively affected by parasitic capacitances and crow-bar currents, and dynamic logic suffers from high leakage and charge sharing issues.
Innovation Solution
Conditioning logic is introduced, which adds extra transistors to conventional logic circuits to condition the state before each transition, allowing for faster transitions and reduced power dissipation by adjusting transistor sizes and using feedback signals to control the enabling of conditioning transistors, thereby optimizing pull-up and pull-down transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complementary digital logic (CMOS) is used, then circuit robustness is improved, but performance and power dissipation are worsened due to parasitic capacitances and crow-bar currents during logic transitions
Solution Approach 1:
The logic circuit is segmented into primary transistors that perform the logic function and separate conditioning transistors that control the transition characteristics. This segmentation allows independent optimization of robustness (primary transistors) and performance (conditioning transistors), resolving the contradiction between circuit robustness and performance.
Solution Approach 2:
The conditioning transistors are enabled in advance based on feedback signals before the actual logic transition occurs. This preliminary action prepares the circuit for optimal transition by pre-positioning the conditioning transistors in the appropriate state, reducing the impact of parasitic capacitances and crow-bar currents during the critical transition period.
2Productivity
If dynamic logic is used, then performance is improved due to smaller parasitic capacitances and fast transitions, but circuit robustness is worsened due to high leakage and charge sharing issues
Solution Approach 1:
The conditioning transistors act as intermediaries between the primary logic transistors and the load. They mediate the transition process by controlling when and how the primary transistors drive the output, enabling fast transitions like dynamic logic while maintaining the robustness of complementary logic through proper timing control via feedback signals.
3Productivity
If transistor sizes are increased to speed up transitions, then performance is improved, but power dissipation due to crow-bar current increases
Solution Approach 1:
Different transistor sizes are assigned to different functions: primary transistors are sized for robust logic operation while conditioning transistors are sized specifically for fast transitions. The conditioning transistors are locally optimized for speed in their specific region of the circuit, allowing overall performance improvement without proportionally increasing power dissipation across the entire circuit.
Solution Approach 2:
The conditioning transistors are activated periodically only during transition periods rather than continuously. Feedback signals detect when transitions are needed and enable the conditioning transistors only at those moments, creating a periodic action pattern that reduces average power dissipation while maintaining fast transition capability when needed.
4Productivity
If conditioning transistors are added to optimize transitions, then performance and power dissipation are improved, but device complexity increases
Solution Approach 1:
The conditioning transistors serve multiple functions: they speed up transitions, reduce crow-bar current, and can be controlled by feedback signals that utilize existing logic outputs. This multi-functionality justifies the added complexity by providing multiple benefits from a single added component rather than requiring separate circuits for each function.
Solution Approach 2:
Feedback signals from existing logic outputs are used to control the conditioning transistors, creating a self-regulating system. The feedback mechanism automatically enables or disables the conditioning transistors based on the actual logic state, reducing the need for additional control logic and minimizing the increase in overall circuit complexity while maintaining optimal performance.
Data Source
AI summary
Conditioning logic modifies the electrical characteristics of conventional logic circuits to improve speed, power, and timing margins. This is accomplished by adding circuitry to pre-condition the state of the circuit to optimize any desired transition. Basic functionality of the logic circuit in response to the inputs is unchanged, but output delays, power dissipation, and timing margins can be improved and other characteristics of the circuit can also be controlled by the conditioning circuitry such as voltage levels, leakage current and power dissipation. The effect of the conditioning circuitry on the electrical and timing parameters of the logic function is controlled by binary feedback inputs to the conditioning circuitry. Feedback inputs can be generated from any combination of logic states and clock inputs including clock inputs and logic inputs not used in the logic function receiving the feedback input.