Conducting Structure Segmentation for Parasitic Capacitance Reduction

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Solution Overview

Problem

Existing semiconductor-on-insulator (SOI) devices face issues with parasitic capacitance due to polycrystalline silicon connections in the active region, leading to resistor-capacitor (RC) delay in conductive lines.

Innovation Solution

The semiconductor device incorporates a substrate with deep trench isolation regions and implant regions of opposite conductivity types, with a conducting structure that separates electrodes and is partially located on these isolation regions, reducing parasitic capacitance and improving RC delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polycrystalline silicon connections are used in the active region, then electrical connectivity is achieved, but parasitic capacitance increases causing RC delay

Engineering Contradiction:

Improveelectrical connectivityVSAvoidRC delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the conducting structure into multiple parts: a first portion over the active region and a second portion over the isolation region. This segmentation allows the conducting structure to maintain electrical connectivity while reducing parasitic capacitance by separating the conductive path from the active region, thereby reducing RC delay in the integrated circuit.

Inventive Principle:

Principle #1Segmentation

2Reliability

If conducting structure is placed on active region, then electrical connectivity is maintained, but parasitic capacitance increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidparasitic capacitance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an isolation region as an intermediary between the conducting structure and the active region. The conducting structure is positioned over this isolation region, which acts as a mediator to reduce parasitic capacitance while still allowing the conducting structure to perform its electrical connectivity function through the first portion that contacts the active region.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10910469B2Semiconductor device with conducting structure for reducing parasitic capacitance and improving RC delay

Publication Date: 2021.02.02 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

AI summary

A semiconductor device includes a substrate and a conducting structure. The substrate has a first conductivity type and includes a first isolation region, a first implant region, and a second implant region. The first isolation region is disposed along the circumference of the substrate. The first implant region has the first conductivity type, and the second implant region has a second conductivity type that is the opposite of the first conductivity type. The conducting structure is disposed on the substrate, and at least a portion of the conducting structure is located on the first isolation region.