Conductive Air Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional methods for forming air spacers in integrated circuit devices fail to effectively reduce parasitic capacitance, which affects device performance due to limitations in dielectric materials and processing techniques.
Innovation Solution
The formation of air spacers is achieved by creating a sacrificial spacer around conductive features, followed by the deposition of an inhibitor material and a metal cap to seal the air spacers, which reduces parasitic capacitance and improves device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used to fill spaces between metal lines, then manufacturing process is simple, but parasitic capacitance is high which reduces device performance
Solution Approach 1:
The patent extracts the dielectric material from the spaces between metal lines, creating air gaps instead. This is achieved by selectively removing dielectric material between adjacent metal lines while leaving dielectric material elsewhere, thereby reducing parasitic capacitance without significantly complicating the manufacturing process
Solution Approach 2:
The patent changes the dielectric constant parameter from conventional values (k>2.5) to air (k=1.0) in specific regions between metal lines. This parameter change directly reduces parasitic capacitance while the selective formation process keeps manufacturing complexity manageable
2Reliability
If air spacers are formed by removing dielectric material between metal lines, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning of the dielectric material removal regions before actual removal. Hard masks are formed with precise patterns that define where air gaps will be created, ensuring manufacturing precision is achieved through careful mask design and selective etching processes
Solution Approach 2:
The patent uses hard mask layers as intermediaries to control the air spacer formation process. These masks enable precise definition of air gap locations and dimensions, transferring the precision requirement from the air gap formation itself to the mask patterning process, which is more controllable
3Reliability
If larger air spacer volumes are created, then parasitic capacitance is further reduced, but risk of shorting between adjacent metal lines increases
Solution Approach 1:
The patent applies different dielectric material configurations to different locations: air gaps are created only in specific regions between metal lines where parasitic capacitance needs reduction, while maintaining dielectric material in other regions for electrical isolation. This local differentiation reduces capacitance without creating shorting paths
4Productivity
If conventional air spacer formation processes are used, then process simplicity is maintained, but manufacturing yield is limited
Solution Approach 1:
The patent combines multiple functions into integrated process steps: air gap formation is merged with existing dielectric removal and metal line formation processes. The selective dielectric removal that creates air gaps is performed using the same etching infrastructure already present in the manufacturing flow, improving yield without proportionally increasing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by utilizing air spacers with a low k-value of 1.0, enhancing device speed and reducing electrical noise, while also allowing for larger air spacer volumes and improved manufacturing yield.
Implementation Method 1
The sacrificial spacer is removed to form an air spacer around the conductive feature
Implementation Method 2
A selective deposition process is then performed to deposit a metal cap on the conductive feature
Implementation Method 3
A selective deposition process is then performed to deposit a metal cap on the conductive feature
Data Source
AI summary
A device includes a first conductive feature in an insulating layer; a dielectric layer over the first conductive feature; a second conductive feature in the dielectric layer, wherein the second conductive feature is over and physically contacting the first conductive feature; an air spacer encircling the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; a metal cap covering the second conductive feature and extending over the air spacer, wherein the air spacer is sealed by a bottom surface of the metal cap; a first etch stop layer on the dielectric layer, wherein a sidewall of the first etch stop layer physically contacts a sidewall of the metal cap; and a second etch stop layer extending on a top surface of the metal cap and a top surface of the first etch stop layer.