Conductive Bump Structure With Graded Insulation for Thermal Stress

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Solution Overview

Problem

Conventional flip-chip packaging methods using metal bumps result in thermal stress that causes peeling forces, leading to cracks in the dielectric and metal layers of semiconductor chips, compromising package reliability.

Innovation Solution

A conductive bump structure comprising a protective layer, insulating layer, and metal layer on a semiconductor substrate, with the insulating layer having varying thickness and width areas to distribute thermal stress, and a metal bump covering only the bonding pad and first area of the insulating layer, while leaving the second area uncovered.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If metal bumps are used for electrical connection in flip-chip packaging, then the electrical conduction path is shortened and package size is reduced, but thermal stress causes peeling forces that crack the dielectric and metal layers

Engineering Contradiction:
Improveelectrical conduction speedVSAvoidpackage reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The insulating layer is designed with varying thickness: a first thickness in the first area (closer to the opening) and a second thickness in the second area (away from the opening), where the second thickness is greater than the first thickness. This local variation in insulating layer thickness creates a stress gradient that distributes thermal stress more evenly, preventing concentration of stress that would cause cracking while maintaining the electrical connection benefits of metal bumps.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the insulating layer has uniform thickness, then manufacturing is simplified, but thermal stress concentrates and causes internal cracks

Engineering Contradiction:
Improveinsulating layer fabricationVSAvoidresistance to thermal stress
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The insulating layer features non-uniform thickness with a first thickness in the first area and a second thickness in the second area, where the second thickness exceeds the first thickness. This local quality variation optimizes stress distribution during thermal compression, preventing crack formation in the dielectric and metal layers while remaining compatible with standard semiconductor manufacturing processes.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The structure effectively reduces thermal stress on the semiconductor substrate, preventing cracks and enhancing package reliability by distributing stress more evenly.

Implementation Method 1

the insulating layer defined with a first area close to the opening and a second area away from the opening, wherein the first area has a first thickness and a first width, the second area has a second thickness and second width, and the second thickness is larger than the first thickness, the second width is larger than the first width

Methodology Applied
Scientific EffectThermal stress distribution: Thermal Expansion

Data Source

PatentUS20250336869A1Conductive bump structure
Publication Date: 2025.10.30 SILICONWARE PRECISION IND CO LTD
  • US20250336869A1 patent drawing
  • US20250336869A1 patent drawing

AI summary

A conductive bump structure is provided, in which a protective layer, an insulating layer, a metal layer, and a metal bump are formed in sequence on a bonding pad of a semiconductor substrate, wherein a thickness and a width of the second area of the insulating layer that is not covered by the metal bump are greater than a thickness and a width of the first area that is covered by the metal bump, respectively. Accordingly, the stress on the semiconductor substrate can be reduced.