Conductive Bump Support Structure for Lower Joint Stress
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes due to the increasing complexity and difficulty of fabrication processes in the semiconductor integrated circuit (IC) industry, where feature sizes continue to decrease.
Innovation Solution
A chip package structure is formed with a conductive bump having a specific configuration, including a conductive layer, alloy layers, and a support layer, where the conductive bump is narrowed through a selective etching process to improve reliability by uniformly sharing joint stress during bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming the conductive bump structure, applying the first mask layer with first pattern, applying the second mask layer with second pattern, and selective etching. This segmentation allows each step to be optimized independently, managing the overall process complexity while achieving advanced feature sizes
Solution Approach 2:
The conductive bump structure is formed in advance before the patterning steps. The first and second mask layers are applied with specific patterns beforehand to guide the subsequent selective etching process. These preliminary actions establish the foundation for achieving precise feature dimensions without increasing the complexity of later steps
2Ease of manufacture
If conventional bonding processes are used with misaligned conductive pads, then manufacturing is simpler, but joint stress and reliability are reduced
Solution Approach 1:
The conductive bump is designed with non-uniform cross-sectional area, creating a neck portion with smaller area between larger first and second portions. This local variation in geometry allows the structure to accommodate misalignment between conductive pads while distributing joint stress more uniformly across the bonding interface, improving reliability without requiring precise alignment
Solution Approach 2:
The cross-sectional area parameter of the conductive bump is varied along its length, transitioning from a uniform cylinder to a structure with a constricted neck portion. This parameter change enables the bump to function as a stress-distributing element that compensates for alignment errors during bonding
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reliability of the chip package structure is enhanced by reducing joint stress and misalignment issues, resulting in improved performance and durability.
Implementation Method 1
the conductive bump is narrowed through a selective etching process
Data Source
AI summary
A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The chip structure includes a support layer over the conductive bump. The support layer is wider than the conductive bump, and a first composition of the support layer is different from a second composition of the conductive bump. The chip structure includes a solder structure over the support layer.