Conductive Bump Layout Compensation for Wafer Height Uniformity
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Solution Overview
Problem
Poor height uniformity of bumps formed on wafers during the wafer bumping process introduces reliability issues and reduces yield rates in semiconductor packaging.
Innovation Solution
Adjusting the forming factor based on environmental density at each formation site to mitigate height deviations by using methods such as adjusting the cross-sectional area, pad size of masks, and exposure energy in the photolithography process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional wafer bumping process is used, then bumps are formed on wafers, but poor height uniformity is introduced
Solution Approach 1:
The patent applies local quality by adjusting the forming factor (cross-sectional area, pad size, exposure energy) based on the environmental density at each specific formation site. This localized adjustment compensates for variations in bump height caused by different local conditions during electroplating, ensuring uniform bump heights across the entire wafer surface.
Solution Approach 2:
The patent implements parameter changes by modifying the forming factor parameters (cross-sectional area, pad size, exposure energy) according to the environmental density at each formation site. These parameter adjustments are made before the electroplating process to pre-compensate for expected height variations, thereby achieving improved bump height uniformity.
2Productivity
If bumps are formed on wafers, then interconnect components are created, but height deviations greater than 10 μm reduce yield rates
Solution Approach 1:
The patent applies preliminary action by adjusting the forming factor parameters before the electroplating process based on pre-calculated environmental density values for each formation site. This pre-adjustment ensures that bumps formed at different locations will achieve uniform heights, preventing yield losses due to height deviations exceeding 10 μm.
Solution Approach 2:
The patent implements feedback by using the environmental density information (calculated from the number of formation sites in surrounding areas) to adjust the forming factor at each location. This feedback mechanism ensures that local variations in plating conditions are compensated, maintaining bump height uniformity across the wafer and improving overall yield rate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves improved inter-bump height uniformity, enhancing the reliability and yield of semiconductor devices by reducing height deviations to less than 10 μm.
Implementation Method 1
adjusting the forming factor based on environmental density at each formation site to mitigate height deviations by using methods such as adjusting the cross-sectional area, pad size of masks, and exposure energy in the photolithography process
Implementation Method 2
conductive bumps simultaneously formed on a plurality of formation sites respectively
Data Source
AI summary
A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.