Conductive Bump Layout Tuning for Wafer Height Uniformity

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Solution Overview

Problem

Poor height uniformity of bumps formed on wafers during the wafer bumping process introduces reliability issues and reduces yield rates in semiconductor packaging due to the loading effect, leading to significant height deviations among the bumps.

Innovation Solution

Adjusting the forming factor based on environmental density at each formation site by altering the cross-sectional area, pad size of the mask, or exposure energy in the photolithography process to ensure uniformity of conductive bumps across the die.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafer bumping is performed using conventional photolithography processes, then the manufacturing process is simple and fast, but the inter-bump height uniformity deteriorates due to the loading effect

Engineering Contradiction:
Improveinter-bump height uniformityVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by adjusting the forming factor (exposure energy, cross-sectional area, or pad size) based on the environmental density at each formation site. Sites with higher environmental density receive different forming factor adjustments compared to sites with lower density, compensating for the loading effect and achieving uniform bump heights across the wafer

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the forming factor parameters (exposure energy, cross-sectional area, or pad size) according to the environmental density at each formation site. This parameter adjustment compensates for variations in environmental density caused by the loading effect, ensuring consistent bump height uniformity across different regions of the wafer

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the forming factor is adjusted based on environmental density, then inter-bump height uniformity is improved, but the photolithography process complexity increases

Engineering Contradiction:
Improvebump height uniformityVSAvoidprocess ease
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing the forming factor for each formation site based on its environmental density before the actual bumping process. This pre-computation allows the photolithography process to proceed with predetermined parameters, reducing real-time complexity while maintaining height uniformity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements local quality by assigning specific forming factors to specific formation sites based on their environmental density characteristics. This localized parameter assignment ensures each site receives optimal exposure conditions while the overall process remains manageable through systematic pre-planning

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Mitigates inter-bump height deviations, enhancing reliability and yield rates by ensuring consistent bump heights, thereby improving the electrical, mechanical, and thermal performance of semiconductor devices.

Implementation Method 1

a photosensitive material layer or a photoresist layer, coated on the conductive layer, wherein the photosensitive material layer or the photoresist layer is patterned to include a first formation site and a second formation site

Methodology Applied
Scientific EffectPhotolithography: Photopolymerisation

Data Source

PatentUS12400987B2Semiconductor device
Publication Date: 2025.08.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12400987B2 patent drawing
  • US12400987B2 patent drawing
  • US12400987B2 patent drawing

AI summary

A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.