Conductive Bump Layout With Misaligned Vias for Bonding Reliability
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Solution Overview
Problem
New packaging technologies for semiconductor dies face manufacturing challenges as they strive to improve density and functionality while maintaining reliability and performance.
Innovation Solution
A semiconductor device structure is developed with conductive bumps and misaligned conductive vias to distribute bonding force evenly, reducing stress and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If new packaging technologies are adopted to improve density and functionality, then device integration increases, but manufacturing challenges and reliability issues worsen
Solution Approach 1:
The patent applies local quality by creating misaligned conductive vias with offset centers relative to the conductive bump centers. This intentional local asymmetry in the via-bump relationship distributes bonding stress non-uniformly, preventing stress concentration at specific points while maintaining overall connection integrity, thus resolving the contradiction between high density packaging and manufacturing reliability
2Ease of manufacture
If conventional aligned conductive via structures are used, then manufacturing process is simple, but stress concentrates at bonding points reducing reliability
Solution Approach 1:
The patent implements asymmetry by deliberately offsetting the centers of conductive vias from the centers of conductive bumps. The via center and bump center are separated by a controlled distance, creating an asymmetric structure that distributes bonding stress across multiple points rather than concentrating it at a single aligned point, thereby improving bonding reliability while maintaining manufacturability
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the interconnection structure, and an upper portion of the conductive pillar is wider than the protruding portion. The semiconductor device structure also includes an upper conductive via positioned vertically between the conductive pillar and the interconnection structure. The semiconductor device structure further includes a lower conductive via positioned vertically between the upper conductive via and the interconnection structure. In a top view, the conductive pillar extends across the upper conductive via and the lower conductive via. In the top view, the upper conductive via is spaced apart from the protruding portion.