Conductive Bump Structure Using Single Patterning Process
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Solution Overview
Problem
The existing flip-chip technique for forming conductive bumps on circuit boards requires multiple patterning processes, limiting pitch reduction and alignment precision, and results in non-uniform solder material height, complicating the manufacturing process and affecting connectivity with external components.
Innovation Solution
A method involving a single patterning process to form conductive bumps on circuit boards, where a patterned trace layer is electroplated, followed by a second resist layer with exposed openings for metal bump formation, and a subsequent adhesive layer, simplifying the process and improving alignment precision and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes are used to form conductive bumps, then alignment precision and pitch control are improved, but device complexity and manufacturing time increase
Solution Approach 1:
The patent combines multiple patterning steps into a single exposure process. The resist layer is exposed once to simultaneously form both the first openings (for electrical connecting pads) and the second openings (for conductive bumps), eliminating the need for separate patterning steps and reducing overall process complexity while maintaining alignment precision
Solution Approach 2:
The electrical connecting pads are formed first as a preliminary step, providing a pre-established conductive structure that serves as the foundation for subsequent bump formation. This preliminary action allows the bumps to be precisely aligned to the pads without requiring additional alignment operations
2Manufacturing precision
If multiple patterning processes are used to form conductive bumps, then alignment precision is improved, but manufacturing time increases
Solution Approach 1:
Multiple patterning operations are merged into a single exposure step. The resist layer is exposed once to define both the electrical connecting pad patterns and the conductive bump patterns simultaneously, reducing the total manufacturing time while achieving the required alignment precision through proper resist and exposure parameter selection
3Productivity
If solder materials are directly formed on electrical connecting pads, then conductive bumps are created, but uniformity of material height is poor
Solution Approach 1:
The patent introduces a trace layer as an intermediary between the electrical connecting pads and the solder materials. This trace layer acts as a controlled intermediate structure that enables more uniform deposition of solder materials, improving height uniformity while maintaining the efficiency of direct bump formation
Solution Approach 2:
The patent adds a vertical dimension to the structure by introducing the trace layer at an intermediate height level. This creates a stepped structure where the trace layer provides a controlled platform for solder deposition, enabling better control over final bump height and uniformity
4Ease of operation
If opening size is enlarged to reduce alignment difficulty, then alignment precision is improved, but pitch between conductive bumps increases
Solution Approach 1:
The patent uses partial exposure action where the resist layer is exposed to form openings that are slightly larger than the final desired bump size. This excessive action in the exposure step is compensated by subsequent etching or resist removal that precisely defines the final opening dimensions, allowing easy alignment while maintaining fine pitch
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for finer pitch conductive bumps with improved uniformity and reduced fabrication costs, enhancing the reliability of electrical connections between the circuit board and external components.
Implementation Method 1
electroplating is performed thereafter so as to form electrical connecting pads 140 (as shown in FIG. 1C) on the first conductive layer 12 within the first openings 130
Data Source
AI summary
A conductive bump structure of a circuit board and a method for forming the same are proposed. A conductive layer is formed on an insulating layer on the surface of the circuit board. A first resist layer is formed on the conductive layer and a plurality of first openings is formed in the first resist layer to expose the conductive layer. Then, a patterned trace layer is electroplated in the first openings and a second resist layer is covered on the circuit board with the patterned trace layer. Second openings are formed in the second resist layer to expose part of the trace layer to be used as electrical connecting pads. Thereafter, metal bumps are electroplated in the second openings and the surface of the circuit board is covered with a solder mask. A thinning process is applied to the solder mask to expose the top surface of the metal bumps. Afterwards, an adhesive layer is formed on the surface of the metal bumps exposing out of the solder mask.