Conductive Bump Step Member for Underfill Flow and Chip Adhesion
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Solution Overview
Problem
Conventional stacked semiconductor packages face issues with decreased operation speed due to signal transmission via wires, increased size, and height, as well as connection failures caused by fillers trapped between bumps, which affect mechanical strength and adhesion.
Innovation Solution
The introduction of conductive bumps with a step member and inclined surface on semiconductor chips, allowing improved flowability of underfill members and enhanced connectivity between stacked semiconductor chips, formed using insulation or conductive substances with optional insulation members.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional wire bonding is used for signal transmission between stacked semiconductor chips, then electrical connection is achieved, but operation speed decreases and package size increases
Solution Approach 1:
The patent extracts and eliminates the wire bonding structure from the stacked semiconductor package, replacing it with direct through-via connections between chips. This removal of the wire bonding layer simplifies the overall structure, reduces signal transmission path length, and improves operation speed while decreasing package height and size.
Solution Approach 2:
The patent transitions from lateral wire bonding connections to vertical through-via connections, changing the dimensional approach of electrical interconnection. By routing signals vertically through the chip stack rather than laterally through wire bonds, the design achieves shorter signal paths and improved performance.
2Reliability
If conventional flat bumps are used for external connections, then connection terminals are formed, but fillers are trapped between bumps causing connection failure and degraded junction strength
Solution Approach 1:
The patent replaces conventional flat bumps with dome-shaped or spherical bump structures for external connections. This curved geometry prevents fillers from being trapped between bumps during chip stacking, as the rounded surfaces allow underfill material to flow smoothly around them. This eliminates connection failures and maintains junction strength while improving reliability.
3Area of stationary object
If through vias are used instead of wire bonding, then additional wire bonding area is eliminated and package size decreases, but bump formation complexity increases
Solution Approach 1:
The patent merges the bump formation process with the existing through-via fabrication process. By integrating dome-shaped bump creation into the through-via manufacturing sequence (using the same plating and shaping steps), the design eliminates the need for separate, complex bump formation operations. This integration simplifies manufacturing while achieving the desired area reduction from eliminating wire bonding.
Data Source
AI summary
A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the step member and having an inclined surface which is inclined with respect to the connection pad.