Conductive Bump Layout for Stress-Resistant Semiconductor Packaging
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Solution Overview
Problem
New packaging technologies for semiconductor dies face manufacturing challenges due to stress and warpage issues, leading to cracks and delamination in conductive pillars, which affect the reliability and performance of semiconductor devices.
Innovation Solution
The via area of peripheral conductive pillars is designed to be larger than central conductive pillars, with wider protruding portions to distribute stress more evenly, reducing the risk of cracks and delamination, and incorporating a redistribution layer to improve electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If smaller package structures are used to reduce space and height, then productivity and cost efficiency are improved, but stress concentrations and warpage issues increase leading to cracks and delamination
Solution Approach 1:
The patent applies local quality by making the peripheral conductive pillars have larger via areas compared to central conductive pillars. This non-uniform distribution strategically places larger stress-distributing structures at the edges where warpage and stress concentrations are most severe, thereby locally addressing the reliability issue without compromising overall productivity gains from small packaging
2Ease of manufacture
If uniform conductive pillar design is used across the chip, then manufacturing complexity is reduced, but stress distribution is uneven causing cracks at edge and corner regions
Solution Approach 1:
The patent implements asymmetry by designing peripheral conductive pillars with larger via areas than central conductive pillars. This asymmetric design creates wider protruding portions at the periphery that better distribute stress during bonding operations, preventing cracks and delamination at edge and corner regions while maintaining overall manufacturing feasibility
3Reliability
If larger via areas are used for peripheral conductive pillars, then stress distribution is improved and cracks are prevented, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the conductive pillar population into two distinct groups: peripheral conductive pillars with larger via areas and central conductive pillars with standard via areas. This segmentation allows each group to be optimized for its specific location's stress conditions, improving overall bonding reliability while keeping the structural changes localized and manageable rather than uniformly complex across the entire device
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first conductive structure over the substrate. The first conductive structure has a first protruding portion extending towards the substrate from a lower surface of the first conductive structure. The semiconductor device structure also includes a second conductive structure over the substrate. The second conductive structure is substantially as wide as the first conductive structure. The second conductive structure has a second protruding portion extending towards the substrate from a lower surface of the second conductive structure. The first conductive structure is closer to a center point of the substrate than the second conductive structure, and the second protruding portion and the first protruding portion have different widths.