Conductive Bus Bar for Uniform Copper Plating on Resistive Substrates
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Solution Overview
Problem
Advanced node technology in CMOS scaling leads to resistance deltas between the wafer edge and center due to pattern density and reduced copper seed thickness, causing non-uniform plating and planarization issues, resulting in poor reliability and yield loss.
Innovation Solution
A method involving the formation of continuous trenches along scribe lines on a semiconductor substrate, metallized to serve as a bus bar, providing a lower resistance conductive path for uniform copper deposition and minimizing resistance differences across the wafer surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional bus bar metallization is used at advanced nodes, then copper seed thickness is reduced for scaling, but resistance delta between wafer edge and center increases
Solution Approach 1:
The bus bar is segmented into multiple discrete metallized regions positioned at strategic locations across the wafer surface. These segmented bus bars are connected through the substrate to form a distributed network that reduces current path length and minimizes resistance delta between wafer edge and center, solving the problem of increased resistance with scaled copper seed thickness.
2Productivity
If plating is performed on resistive seed substrate, then copper deposition occurs, but terminal effect causes non-uniform plating distribution
Solution Approach 1:
Multiple bus bars are positioned across the wafer surface to create equipotential regions that equalize the electrical potential distribution. This reduces the terminal effect by minimizing potential gradients across the substrate, resulting in uniform current density distribution and consistent copper plating thickness across the entire wafer surface.
3Reliability
If continuous metallized trenches are formed along scribe lines, then resistance delta is minimized, but process complexity increases
Solution Approach 1:
The metallized trenches along scribe lines serve multiple functions: they act as bus bars for electrical connection, provide mechanical support structures, and serve as alignment references for subsequent processing steps. This multi-functionality reduces the need for separate structures, thereby minimizing process complexity while achieving resistance uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform copper deposition, reduces embedded voids, and enhances reliability by minimizing the 'terminal effect' and CMP under-polish issues, leading to improved yield and planarization.
Implementation Method 1
the electrical contact for the plating process is conducted through the edge of the wafer... scaling of the barrier seed on advance node causes reduction of effective copper seed thickness... huge resistance delta between wafer edge and center
Implementation Method 2
When plating onto resistive substrates, the potential drop across the wafer surface can cause non-uniformities in the current density distribution. This so-called 'terminal effect' leads to a naturally higher deposition rate at the wafer edge compared to the center.
Data Source
AI summary
A method includes providing a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, and forming a metallic structure on the semiconductor substrate to serve as a bus bar for the printed circuits and/or semiconductor devices. A semiconductor structure is realized with the method, the semiconductor structure including a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, a metallic structure on the semiconductor substrate serving as a bus bar for the printed circuits and/or semiconductor devices, and printed circuits and/or semiconductor devices in the semiconductor areas.